Resistive memory device

Patent metadata

Field	Value
Publication number	US-12324166-B2
Application number	US-202217568866-A
Country	US
Kind code	B2
Filing date	Jan 5, 2022
Priority date	Jun 16, 2021
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A resistive memory device including a resistive memory pattern; and a selection element pattern electrically connected to the resistive memory pattern, the selection element pattern including a chalcogenide switching material and at least one metallic material, the chalcogenide switching material including germanium, arsenic, and selenium, and the at least one metallic material including aluminum, strontium, or indium, wherein the selection element pattern includes an inhomogeneous material layer in which content of the at least one metallic material in the selection element pattern is variable according to a position within the selection element pattern.

First claim

What is claimed is:

1. A resistive memory device, comprising:
a resistive memory pattern; and
a selection element pattern electrically connected to the resistive memory pattern, the selection element pattern including a chalcogenide switching material and at least one metallic material, the chalcogenide switching material including germanium, arsenic, and selenium, and the at least one metallic material including aluminum, strontium, or indium,
wherein the selection element pattern includes an inhomogeneous material layer in which content of the at least one metallic material in the selection element pattern is variable according to a position within the selection element pattern.

2. The resistive memory device as claimed in claim 1 , wherein:
the selection element pattern includes a compound represented by Formula 1:
Ge x As y Se z (M1) a   [Formula 1]

in Formula 1,
M1 is aluminum or strontium, and
0.13≤x≤0.23, 0.25≤y≤0.35, 0.38≤z≤0.50, 0.001≤a≤0.06, and x+y+z+a=1.

3. The resistive memory device as claimed in claim 1 , wherein the selection element pattern includes a compound represented by Ge x As y Se z Al a , in which 0.13≤x≤0.23, 0.25≤y≤0.35, 0.38≤z≤0.50, 0.001≤a≤0.06, and x+y+z+a=1.

4. The resistive memory device as claimed in claim 1 , wherein the selection element pattern includes a compound represented by Ge x As y Se z Sr a , in which 0.13≤x≤0.23, 0.25≤y≤0.35, 0.38≤z≤0.50, 0.001≤a≤0.06, and x+y+z+a=1.

5. The resistive memory device as claimed in claim 1 , wherein:
the selection element pattern includes a compound represented by Formula 2:
Ge x As y Se z (M1) a (M2) b   [Formula 2]

in Formula 2,
M1 is aluminum or strontium,
M2 is indium, and
0.13≤x≤0.23, 0.25≤y≤0.35, 0.38≤z≤0.50, 0.001≤a≤0.08, 0.001≤b≤0.06, and x+y+z+a+b=1.

6. The resistive memory device as claimed in claim 1 , wherein the selection element pattern includes a compound represented by Ge x As y Se z Al a In b , in which 0.13≤x≤0.23, 0.25≤y≤0.35, 0.38≤z≤0.50, 0.001≤a≤0.08, 0.001≤b≤0.06, and x+y+z+a+b=1.

7. The resistive memory device as claimed in claim 1 , wherein the selection element pattern includes a compound represented by Ge x As y Se z Sr a In b , in which 0.13≤x≤0.23, 0.25≤y≤0.35, 0.38≤z≤0.50, 0.001≤a≤0.08, 0.001≤b≤0.06, and x+y+z+a+b=1.

8. The resistive memory device as claimed in claim 1 , wherein:
the selection element pattern further includes tungsten, titanium, or copper, and
a content of the tungsten, titanium, or copper in the selection element pattern is more than 0 atomic percent (at %) and less than 2 at %.

9. The resistive memory device as claimed in claim 1 , wherein:
the selection element pattern includes a plurality of chalcogenide layers having different compositions,
the plurality of chalcogenide layers include a first chalcogenide layer and a second chalcogenide layer, which are at different heights from the resistive memory pattern,
the first chalcogenide layer does not include aluminum and does not include strontium, and
the second chalcogenide layer includes aluminum or strontium.

10. The resistive memory device as claimed in claim 1 , wherein:
the selection element pattern includes a plurality of chalcogenide layers having different compositions,
the plurality of chalcogenide layers include a first chalcogenide layer, a second chalcogenide layer, and a third chalcogenide layer, which are at different heights from the resistive memory pattern,
the first chalcogenide layer does not include aluminum,
the second chalcogenide layer includes a first content of aluminum, and
the third chalcogenide layer includes a second content of aluminum, the second content being different from the first content.

11. The resistive memory device as claimed in claim 1 , wherein the resistive memory pattern includes a chalcogenide material having a different composition from the chalcogenide switching material.

12. A resistive memory device, comprising:
a first conductive line extending lengthwise in a first lateral direction on a substrate;
a second conductive line extending lengthwise in a second lateral direction on the substrate, the second lateral direction intersecting with the first lateral direction; and
a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell being connected between the first conductive line and the second conductive line,
wherein the memory cell includes:
a resistive memory pattern; and
a selection element pattern electrically connected to the resistive memory pattern, the selection element pattern includes a chalcogenide switching material and a metallic material, the chalcogenide switching material including germanium, arsenic, and selenium, and the metallic material including aluminum, strontium, or indium, and

wherein the selection element pattern includes an inhomogeneous material layer in which content of the metallic material is variable according to a position within the selection element pattern.

13. The resistive memory device as claimed in claim 12 , wherein:
the selection element pattern includes a compound represented by Formula 1:
Ge x As y Se z (M1) a   [Formula 1]

in Formula 1,
M1 is aluminum or strontium, and
0.13≤x≤0.23, 0.25≤y≤0.35, 0.38≤z≤0.50, 0.001≤a≤0.06, and x+y+z+a=1.

14. The resistive memory device as claimed in claim 12 , wherein:
the selection element pattern includes a compound represented by Formula 2:
Ge x As y Se z (M1) a (M2) b   [Formula 2]

in Formula 2,
M1 is aluminum or strontium,
M2 is indium, and
0.13≤x≤0.23, 0.25≤y≤0.35, 0.38≤z≤0.50, 0.001≤a≤0.08, 0.001≤b≤0.06, and x+y+z+a+b=1.

15. The resistive memory device as claimed in claim 12 , wherein:
the selection element pattern further includes tungsten, titanium, or copper, and
a content of the tungsten, titanium, or copper in the selection element pattern is more than 0 atomic percent (at %) and less than 2 at %.

16. The resistive memory device as claimed in claim 12 , wherein:
the selection element pattern includes a plurality of chalcogenide layers having different compositions,
the plurality of chalcogenide layers include a first chalcogenide layer closest to the resistive memory pattern and a second chalcogenide layer farthest from the resistive memory pattern,
the first chalcogenide layer does not include aluminum and does not include strontium, and
the second chalcogenide layer includes aluminum or strontium.

17. The resistive memory device as claimed in claim 12 , wherein:
the selection element pattern includes a plurality of chalcogenide layers having different compositions,
the plurality of chalcogenide layers include a first chalcogenide layer, a second chalcogenide layer, and a third chalcogenide layer, which are at different heights from the resistive memory pattern,
the first chalcogenide layer does not include aluminum,
the second chalcogenide layer includes a first content of aluminum, and
the third chalcogenide layer includes a second content of aluminum, the second content being different from the first content.

18. A resistive memory device, comprising:
a first conductive line extending lengthwise in a first lateral direction on a substrate;
a plurality of second conductive lines extending lengthwise in a second lateral direction on the substrate, the plurality of second conductive lines being spaced apart from the first conductive line in a vertical direction, the second lateral direction intersecting with the first lateral direction;
a plurality of memory cells at a plurality of in

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Chungman
• Koo Bonwon
• Ahn Dongho
• Yang Kiyeon
• Wu Zhe
• Lee Chang Seung

Classifications

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10B63/10

  Phase change RAM [PCRAM, PRAM] devices · CPC title

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10N70/8825

  Selenides, e.g. GeSe · CPC title

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title