Semiconductor device with capping conductive layer on an electrode and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12324145-B2
Application number	US-202318136984-A
Country	US
Kind code	B2
Filing date	Apr 20, 2023
Priority date	Jun 3, 2020
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A semiconductor device includes conductive pillars on a semiconductor substrate, a first support pattern that contacts first portions of lateral surfaces of the conductive pillars and connects the conductive pillars to each other, the first support pattern including first support holes that expose second portions of the lateral surfaces of the conductive pillars, a capping conductive pattern that contacts the second portions of the lateral surfaces of the conductive pillars and exposes the first support pattern, the second portions of the lateral surfaces of the conductive pillars being in no contact with the first support pattern, and a dielectric layer that covers the first support pattern and the capping conductive pattern, the dielectric layer being spaced apart from the conductive pillars.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a first mold layer and a first support layer on a substrate;
forming a first conductive pillar that penetrates the first mold layer and the first support layer;
etching the first support layer to form a first support pattern having a first support hole that exposes the first mold layer, the first support pattern contacting a first side surface of the first conductive pillar;
exposing a second side surface of the first conductive pillar by removing the first mold layer through the first support hole;
forming a capping conductive pattern that covers the second side surface of the first conductive pillar;
after forming the capping conductive pattern, forming a dielectric layer on the capping conductive pattern; and
forming a top electrode on the dielectric layer.

2. The method as claimed in claim 1 ,
wherein forming the capping conductive pattern includes performing an area selective deposition process to provide a metal precursor that has a low chemical affinity to a surface of the first support pattern and a high chemical affinity to the second side surface of the first conductive pillar.

3. The method as claimed in claim 2 ,
wherein performing the area selective deposition process includes:
adsorbing the metal precursor on the second side surface of the first conductive pillar;
forming a single-atom metal layer; and
purging a gas.

4. The method as claimed in claim 1 ,
wherein a thickness of an edge of the capping conductive pattern decreases as a distance from the first support pattern decreases.

5. The method as claimed in claim 1 ,
wherein the dielectric layer is spaced apart from the first conductive pillar.

6. The method as claimed in claim 1 , further comprising:
before forming the first conductive pillar, forming a second mold layer and a second support layer on the first support layer;
etching the second support layer to form a second support pattern including a second support hole; and
removing the second mold layer,
wherein the capping conductive pattern is formed to expose the second support pattern.

7. The method as claimed in claim 1 , further comprising forming a sacrificial layer that fills an interior of the first conductive pillar,
wherein removing the first mold layer includes removing the sacrificial layer.

8. The method as claimed in claim 1 , further comprising:
before forming the first support pattern, forming a second mold layer and a second support layer on the first support layer;
forming a second conductive pillar that penetrates the second support layer and the second mold layer, the second conductive pillar contacting the first conductive pillar;
etching the second support layer to form a second support pattern having a second support hole; and
removing the second mold layer to expose a third side surface of the second conductive pillar,
wherein the capping conductive pattern exposes the second support pattern and covers the third side surface of the second conductive pillar, and
wherein the second support pattern is in contact with a fourth side surface of the second conductive pillar.

9. The method as claimed in claim 1 , further comprising:
before forming the first mold layer and the first support layer, forming an interlayer insulating layer on the substrate; and
forming an etch stop layer on the interlayer insulating layer.

10. A method of fabricating a semiconductor device, the method comprising:
forming a plurality of mold layers and a plurality of support layers on a substrate;
forming a plurality of conductive pillars penetrating the plurality of mold layers and the plurality of support layers;
forming a plurality of support patterns by patterning the plurality of support layers, each of the plurality of support patterns having a support hole that exposes at least three of the plurality of conductive pillars;
exposing a side surface of each of the plurality of conductive pillars by removing the plurality of mold layers through the support hole of each of the plurality of support patterns;
forming a capping conductive pattern on the side surface of each of the plurality of conductive pillars;
after forming the capping conductive pattern, forming a dielectric layer on the capping conductive pattern; and
forming a top electrode on the dielectric layer,
wherein each of the plurality of conductive pillars includes titanium nitride (TiN), and the capping conductive pattern includes niobium (Nb).

11. The method as claimed in claim 10 ,
wherein forming the capping conductive pattern includes performing an area selective deposition process in a plurality of process cycles.

12. The method as claimed in claim 11 ,
wherein each of the plurality of process cycles includes:
providing a source gas;
providing a reaction gas; and
purging the source gas and the reaction gas.

13. The method as claimed in claim 11 ,
wherein a number of the plurality of process cycles is less than or equal to about 70.

14. The method as claimed in claim 10 ,
wherein the plurality of support layers have different thicknesses from each other.

15. The method as claimed in claim 10 ,
wherein the capping conductive pattern is spaced apart from the plurality of support patterns.

16. The method as claimed in claim 10 ,
wherein a thickness of an edge of the capping conductive pattern decreases as a distance from the plurality of support patterns decreases.

17. The method as claimed in claim 10 ,
wherein the plurality of mold layers have different thicknesses from each other.

18. The method as claimed in claim 10 , further comprising forming an etch stop layer on the substrate, before forming the plurality of mold layers and the plurality of support layers,
wherein the capping conductive pattern exposes a top surface of the etch stop layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Woo Chang-Su
• Kim Haeryong
• Kim Younsoo
• Moon Sunmin
• Song Jeonggyu
• Jung Kyooho

Classifications

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title

• H10B12/318

  the storage electrode having multiple segments · CPC title