Integrated power management cells for gate all around technologies

Patent metadata

Field	Value
Publication number	US-12323142-B2
Application number	US-202318504062-A
Country	US
Kind code	B2
Filing date	Nov 7, 2023
Priority date	Nov 7, 2023
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

At least one integrated power management cell of an IC includes a first cell, which is a 4-height cell, that includes a first continuous n-well, a first power interconnect coupled to a first voltage source associated with a first voltage domain and to the first continuous n-well, a second continuous n-well, a second power interconnect coupled to a second voltage source associated with a second voltage domain and to the second continuous n-well, a first subset of a first voltage level shifter associated with the first voltage domain and coupled to the first power interconnect, and a second subset of the first voltage level shifter associated with the second voltage domain and coupled to the second power interconnect.

First claim

What is claimed is:

1. At least one integrated power management cell of an integrated circuit (IC), comprising:
a first cell, the first cell being a 4-height cell, the first cell including a first row, a second row, a third row, and a fourth row,
the first cell comprising:
a first continuous n-type well (n-well) extending in a first direction across portions of the first row and the second row of the first cell to edges of the first cell;
a first power interconnect extending in the first direction along edges of both the first row and the second row of the first cell, the first power interconnect being coupled to a first voltage source associated with a first voltage domain and to the first continuous n-well;
a second continuous n-well extending in the first direction across portions of the third row and the fourth row of the first cell to edges of the first cell;
a second power interconnect extending in the first direction along edges of both the third row and the fourth row of the first cell, the second power interconnect being coupled to a second voltage source associated with a second voltage domain and to the second continuous n-well;
a first subset of a first voltage level shifter in one of the first row or the second row of the first cell, the first subset of the first voltage level shifter being associated with the first voltage domain and coupled to the first power interconnect; and
a second subset of the first voltage level shifter in one of the third row or the fourth row of the first cell, the second subset of the first voltage level shifter being associated with the second voltage domain and being coupled to the second power interconnect.

2. The at least one integrated power management cell of the IC of claim 1 , wherein the first cell further comprises:
a first clamp subcell associated with the first voltage domain in one of the first row or the second row of the first cell, the first clamp subcell being coupled to the first power interconnect, wherein the first subset of the first voltage level shifter is in an other one of the first row or the second row of the first cell; and
a second clamp subcell associated with the second voltage domain in one of the third row or the fourth row of the first cell, the second clamp subcell being coupled to the second power interconnect, wherein the second subset of the first voltage level shifter is in an other one of the third row or the fourth row of the first cell.

3. The at least one integrated power management cell of the IC of claim 1 , wherein the first voltage source is an input voltage drain to drain (VDD) voltage source, and the second voltage source is an output VDD voltage source.

4. The at least one integrated power management cell of the IC of claim 2 , wherein the first cell further comprises:
a third power interconnect extending in the first direction along an edge of the first row of the first cell, the third power interconnect being coupled to a third voltage source;
a fourth power interconnect extending in the first direction along edges of both the second row and the third row of the first cell, the fourth power interconnect being coupled to the third voltage source; and
a fifth power interconnect extending in the first direction along an edge of the fourth row of the first cell, the fifth power interconnect being coupled to the third voltage source,
wherein the first clamp subcell is coupled to one of the third power interconnect or the fourth power interconnect, and the first subset of the first voltage level shifter is coupled to an other one of the third power interconnect or the fourth power interconnect, and
wherein the second clamp subcell is coupled to one of the fourth power interconnect or the fifth power interconnect, and the second subset of the first voltage level shifter is coupled to an other one of the fourth power interconnect or the fifth power interconnect.

5. The at least one integrated power management cell of the IC of claim 4 , wherein the third voltage source is a voltage source supply (VSS) voltage source.

6. The at least one integrated power management cell of the IC of claim 4 , wherein the first cell further comprises:
a logic subcell associated with the first voltage domain, the logic subcell being adjacent the first clamp subcell in one of the first row or the second row of the first cell, the logic subcell being coupled to the first power interconnect and one of the third power interconnect or the fourth power interconnect.

7. The at least one integrated power management cell of the IC of claim 4 , wherein the second clamp subcell is an always-on subcell.

8. The at least one integrated power management cell of the IC of claim 4 , wherein the first cell further comprises:
an always-on subcell associated with the second voltage domain, the always-on subcell being adjacent the second clamp subcell in one of the third row or the fourth row of the first cell, the always-on subcell being coupled to the second power interconnect and one of the fourth power interconnect or the fifth power interconnect.

9. The at least one integrated power management cell of the IC of claim 4 , wherein:
the first clamp subcell is in the first row of the first cell, the first clamp subcell being coupled to the third power interconnect;
the first subset of the first voltage level shifter is in the second row of the first cell, the first subset of the first voltage level shifter being coupled to the fourth power interconnect;
the second clamp subcell is in the third row of the first cell, the second clamp subcell being coupled to the fourth power interconnect; and
the second subset of the first voltage level shifter is in the fourth row of the first cell, the second subset of the first voltage level shifter being coupled to the fifth power interconnect.

10. The at least one integrated power management cell of the IC of claim 9 , wherein the first cell further comprises:
a logic subcell associated with the first voltage domain, the logic subcell being adjacent the first clamp subcell in the first row of the first cell, the logic subcell being coupled to the first power interconnect and the third power interconnect; and
an always-on subcell associated with the second voltage domain, the always-on subcell being adjacent the second clamp subcell in the third row of the first cell, the always-on subcell being coupled to the second power interconnect and the fourth power interconnect.

11. The at least one integrated power management cell of the IC of claim 4 , wherein:
the first subset of the first voltage level shifter is in the first row of the first cell, the first subset of the first voltage level shifter being coupled to the third power interconnect;
the first clamp subcell is in the second row of the first cell, the first clamp subcell being coupled to the fourth power interconnect;
the second clamp subcell is in the third row of the first cell, the second clamp subcell being coupled to the fourth power interconnect; and
the second subset of the first voltage level shifter is in the fourth row of the first cell, the second subset of the first voltage level shifter being coupled to the fifth power interconnect.

12. The at least one integrated power management cell of the IC of claim 11 , wherein the first cell further comprises:
a logic subcell associated with the first voltage domain, the logic subcell being adjacent the first clamp subcell in the second row of the first cell, the logic subcell being coupled to the first power interconnect and the fourth power interconnect; and
an always-on subcell associated with the second voltage domain, the always-on subcell being adj

Assignees

• Qualcomm Inc

Inventors

• Vilangudipitchai Ramaprasath
• Narayanan Venkat
• Samson Giby
• Boynapalli Venugopal

Classifications

• H03K3/356113

  using additional transistors in the input circuit · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H10D84/851

  comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title

• H10D89/10

  Integrated device layouts · CPC title