Vertical power grid standard cell architecture

Patent metadata

Field	Value
Publication number	US-11710733-B2
Application number	US-202016808336-A
Country	US
Kind code	B2
Filing date	Mar 3, 2020
Priority date	Mar 3, 2020
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every m th track, where 2≤m<P PG and P PG is a PG grid pitch. A MOS IC may include at least one MOS IC logic cell, and may further include a first set of PG Mx layer interconnects extending in the first direction over the at least one logic cell. The first set of PG Mx layer interconnects have the pitch P PG >m*P.

First claim

What is claimed is:

1. A metal oxide semiconductor (MOS) integrated circuit (IC) logic cell, comprising:
a plurality of gate interconnects extending on tracks in a first direction orthogonal to a second direction; and
intra-cell routing interconnects coupled to at least a subset of the gate interconnects, the intra-cell routing interconnects including intra-cell metal x (Mx) layer interconnects on an Mx layer extending in the first direction, the Mx layer being a lowest first direction metal layer for power and ground (PG) that also extends in the first direction, the intra-cell Mx layer interconnects extending in the first direction over at least a subset of the tracks excluding every m th track, where m is an integer greater than or equal to 2 and less than P PG , and P PG is a PG grid pitch.

2. The MOS IC logic cell of claim 1 , wherein the plurality of gate interconnects include n gate interconnects, where n is an integer, and the intra-cell Mx layer interconnects do not extend over any portion of every other m th track.

3. The MOS IC logic cell of claim 2 , wherein the intra-cell Mx layer interconnects do not extend over any portion of an k+i*m track for i=0, 1, . . . , j, where k is an integer, and j is a largest integer such that k+j*m is less than or equal to n.

4. The MOS IC logic cell of claim 1 , wherein m is an integer less than or equal to 3.

5. The MOS IC logic cell of claim 4 , wherein m is equal to 2, and the intra-cell Mx layer interconnects do not extend over any portion of every other gate interconnect of the plurality of gate interconnects.

6. The MOS IC logic cell of claim 1 , wherein the Mx layer is an M2 layer.

7. The MOS IC logic cell of claim 1 , wherein the tracks are separated by a pitch P.

8. The MOS IC logic cell of claim 1 , wherein the intra-cell Mx layer interconnects are unidirectional in the first direction.

9. The MOS IC logic cell of claim 1 , wherein the intra-cell routing interconnects further include intra-cell metal x−1 (Mx−1) layer interconnects on an Mx−1 layer extending in the second direction.

10. The MOS IC logic cell of claim 9 , wherein the Mx−1 layer is an M1 layer.

11. The MOS IC logic cell of claim 9 , wherein the Mx−1 layer interconnects are unidirectional in the second direction.

12. The MOS IC logic cell of claim 1 , wherein P PG is equal to 10.

Assignees

• Qualcomm Inc

Inventors

• Lim Hyeokjin
• Chava Bharani
• Vang Foua
• Kang Seung Hyuk
• Boynapalli Venugopal

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10D84/975

  Wiring regions or routing · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H01L27/0207 Primary

  Electricity · mapped topic