Area-optimized retention flop implementation

Patent metadata

Field	Value
Publication number	US-2017194949-A1
Application number	US-201514986444-A
Country	US
Kind code	A1
Filing date	Dec 31, 2015
Priority date	Dec 31, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

An integrated circuit device having a p-well plane, a plurality of substantially parallel n-well rows, and a logic cell. The p-well plane is comprised of p-type semiconductor material. Each n-well row comprises an n-type layer disposed on the surface of the p-well plane. The plurality of n-well rows includes a first n-well row and a second n-well row. The logic cell is arranged on the p-well plane and the footprint of the logic cell encompasses both the first and second n-well rows.

First claim

1 . An integrated circuit device comprising:
a p-well plane comprising p-type semiconductor material; a plurality of substantially parallel n-well rows, each n-well row comprising an n-type layer disposed on the surface of the p-well plane, the plurality of n-well rows comprising a first n-well row and a second n-well row, wherein the first n-well row is coupled to a switchable power supply and the second n-well row is coupled to an always-on power supply; and a first logic cell arranged on the p-well plane, the footprint of the logic cell encompassing both the first and second n-well rows.

2 . The integrated circuit device of claim 1 wherein the first n-well row is coupled to a first power supply and the second n-well row is coupled to a second power supply.

3 . (canceled)

4 . The integrated circuit device of claim 1 wherein the first logic cell comprises at least one transistor having a first voltage threshold and at least one transistor having a second voltage threshold, the at least one transistor having the first voltage threshold utilizing the first n-well row and the at least one transistor having the second voltage threshold utilizing the second n-well row.

5 . An integrated circuit device comprising:
a p-well plane comprising p-type semiconductor material; a plurality of substantially parallel n-well rows, each n-well row comprising an it-type layer disposed on the surface of the p-well plane, the plurality of n-well rows comprising a first n-well row and a second n-well row; a first logic cell arranged on the p-well plane, the footprint of the loge cell encompassing both the first and second n-well rows; wherein the first logic cell comprises at least one transistor having a first voltage threshold and at least one transistor having a second voltage threshold, the at least one transistor having the first voltage threshold utilizing the first n-well row and the at least one transistor having the second voltage threshold utilizing the second n-well row; and wherein the first logic cell comprises at least one standard-voltage-threshold (SVT) transistor and at least one high-voltage-threshold (HVT) transistor, the at least one SVT transistor utilizing the first n-well row and the at least one HVT transistor utilizing the second n-well row.

6 . An integrated circuit device comprising:
a p-well plane comprising p-type semiconductor material; a plurality of substantially parallel n-well rows, each n-well row comprising an n-type layer disposed on the surface of the p-well plane, the plurality of n-well rows comprising a first n-well row and a second n-well row; a first logic cell arranged on the p-well plane, the footprint of the logic cell encompassing both the first and second n-well rows; and first, second, third and fourth parallel and contiguous logic cell rows, wherein the first and second logic cell rows are parallel to and share the first n-well row, and the third and fourth logic cell rows are parallel to and share the second n-well row, and wherein the footprint of the first logic cell encompasses the first, second, third and fourth logic cell rows.

7 . An integrated circuit device comprising:
a p-well plane comprising p-type semiconductor material; a plurality of substantially parallel n-well rows, each n-well row comprising an n-type layer disposed on the surface of the p-well plane, the plurality of n-well rows comprising a first n-well row and a second n-well row; a first logic cell arranged on the p-well plane, the footprint of the logic cell encompassing both the first and second n-well rows; and a second logic cell arranged on the p-well plane adjacent to the first logic cell, the footprint of the second logic cell encompassing both the first and second n-well rows and encompassing the first, second, third and fourth logic cell rows.

8 . An integrated circuit device comprising:
a p-well plane comprising p-type semiconductor material; a plurality of substantially parallel n-well rows, each a-well row comprising an n-type layer disposed on the surface of the p-well plane, the plurality of n-well rows comprising a first n-well row and a second n-well row; and a first logic cell arranged on the p-well plane, the footprint of the logic cell encompassing both the first and second n-well rows wherein the first logic cell comprises a retention flop.

9 . The integrated circuit of claim 8 wherein said retention flop comprises a master latch and a slave latch, the master latch comprising at least one SVT transistor that utilizes the first n-well row, and the slave latch comprising at least one HVT transistor that utilizes the second n-well row.

10 . An integrated circuit logic cell comprising:
a p-well plane comprising p-type semiconductor material; a first n-well row comprising an n-type layer disposed on the surface of the p-well plane; a second n-well row substantially parallel to the first n-well row and comprising an n-type layer disposed on the surface of the p-well plane; and first, second, third and fourth parallel and contiguous cell rows, wherein the first and second logic cell rows are parallel to and share the first n-well row, and the third and fourth logic cell rows are parallel to and share the second n-well row.

11 . The integrated circuit logic cell of claim 10 wherein the first n-well row is coupled to a first power supply and the second n-well row is coupled to a second power supply.

12 . The integrated circuit logic cell of claim 10 wherein the first n-well row is coupled to a switchable power supply and the second n-well row is coupled to an always-on power supply.

13 . The integrated circuit logic cell of claim 10 , further comprising at least one transistor having a first voltage threshold and at least one transistor having a second voltage threshold, the at least one transistor having the first voltage threshold utilizing the first n-well row and the at least one transistor having the second voltage threshold utilizing the second n-well row.

14 . The integrated circuit logic cell of claim 10 , further comprising at least one standard-voltage-threshold (SVT) transistor and at least one high-voltage-threshold (HVT) transistor, the at least one SVT transistor utilizing the first n-well row and the at least one HVT transistor utilizing the second n-well row.

15 . The integrated circuit logic cell of claim 10 wherein the logic cell is a retention flop, and wherein said retention flop comprises a master latch and a slave latch, the master latch comprising at least one SVT transistor that utilizes the first n-well row, and the slave latch comprising at least one HVT transistor that utilizes the second n-well row.

16 . An integrated circuit device comprising:
a p-well plane comprising p-type semiconductor material; a plurality of substantially parallel n-well rows, each n-well row comprising an n-type layer disposed on the surface of the p-well plane, the plurality of n-well rows comprising:
a first n-well row coupled to a switchable power supply; and
a second n-well row coupled to an always-on power supply; and
a logic cell arranged on the p-well plane, the footprint of the logic cell encompassing both the first and second n-well rows, the logic cell comprising at least one standard-voltage-threshold (SVT) transistor and at least one high-voltage-threshold (HVT) transistor, the at least one SVT transistor utilizing the first n-well row and the at least one HVT transistor utilizing the second n-well row.

17 . The integrated circuit device of claim 16 , further comprising first, second, third and fourt

Assignees

• Texas Instruments Inc

Inventors

• Srivastava Sudesh Chandra
• Singhal Vivek

Classifications

• H01L27/088

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H03K3/3562 Primary

  of the primary-secondary type · CPC title

• H01L29/1095

  Electricity · mapped topic

• H10D89/10

  Integrated device layouts · CPC title