Large die wafer, large die and method of forming the same

Patent metadata

Field	Value
Publication number	US-12322707-B2
Application number	US-202117566398-A
Country	US
Kind code	B2
Filing date	Dec 30, 2021
Priority date	Jun 11, 2021
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

The present invention provides a large die, a method of forming the large die and a large die wafer. The method includes: providing a wafer containing a plurality of large dies each having a size greater than that of a maximum field of exposure of a stepper, each large die including at least two die portions to be stitched together, the die portions including a substrate and a first metal layer, the first metal layer including at least to-be-interconnected metal layers for interconnection of the die portions; and forming a second metal layer including at least inter-die interconnecting metal layers crossing dummy dicing margins between adjacent die portions and coming into electrical connection with the to-be-interconnected metal layers of the adjacent die portions. The present invention allows interconnection of the die portions to be stitched together in each large die.

First claim

What is claimed is:

1. A method of forming a large die, the method comprising:
providing a wafer comprising a plurality of large dies each having a size greater than a size of a maximum field of exposure of a stepper, each of the large dies comprising at least two die portions to be stitched together, each of the die portions comprising a main die region and dummy dicing margins surrounding the main die region, each of the die portions having a size that is smaller than or equal to the size of the maximum field of exposure of the stepper, the die portions each comprising a substrate, a dielectric layer on the substrate and a first metal layer embedded in the dielectric layer, the first metal layer comprising at least to-be-interconnected metal layers for interconnection of the die portions to be stitched together; and
forming a second metal layer comprising at least inter-die interconnecting metal layers crossing the dummy dicing margins between adjacent ones of the die portions and coming into electrical connection with the to-be-interconnected metal layers of the adjacent ones of the die portions;
wherein the first metal layer further comprises leading-out metal layers in the main die region, wherein the second metal layer further comprises intra-die metal layers in the main die region, and wherein in each die portion, the intra-die metal layers are electrically connected to the leading-out metal layers along a thickness direction of the die portion, and
wherein the first metal layer further comprises first mark metal layers, the to-be-interconnected metal layers, the leading-out metal layers and the first mark metal layers of the first metal layer are formed in a same process.

2. The method of claim 1 , wherein the inter-die interconnecting metal layers comprise first interconnecting sections and second interconnecting sections, the first interconnecting sections disposed in the main die region, the second interconnecting sections crossing the dummy dicing margins between adjacent ones of the die portions and coming into electrical connection with the to-be-interconnected metal layers of the adjacent ones of the die portions.

3. The method of claim 2 , wherein the formation of the second metal layer comprises:
forming a photoresist over the dielectric layer; and
exposing the die portions successively one by one using a first photomask module, the first photomask module having an exposure pattern comprising at least features for the first interconnecting sections in the main die region.

4. The method of claim 2 , wherein the second interconnecting sections comprise X-directional second interconnecting sections and Y-directional second interconnecting sections,
the X-directional second interconnecting sections extending along an X direction and coming into electrical connection with X-directionally extending first interconnecting sections of adjacent ones of the die portions to be stitched together,
the Y-directional second interconnecting sections extending along a Y direction and coming into electrical connection with Y-directionally extending first interconnecting sections of adjacent ones of the die portions to be stitched together.

5. The method of claim 4 , wherein the formation of the second metal layer further comprises:
exposing the X-directional second interconnecting sections of adjacent ones of the die portions on the photoresist successively one by one using a second photomask module, the second photomask module having an exposure pattern comprising at least features for the X-directional second interconnecting sections; and
exposing the Y-directional second interconnecting sections of adjacent ones of the die portions on the photoresist successively one by one using a third photomask module, the second photomask module having an exposure pattern comprising at least features for the Y-directional second interconnecting sections.

6. The method of claim 5 , wherein the formation of the second metal layer further comprises:
performing an etching process on portions of the dielectric layer exposed from the photoresist, which correspond to the first interconnecting sections, the X-directional second interconnecting sections and the Y-directional second interconnecting sections, to form openings in which the first metal layer is exposed;
filling the openings with a metal layer to form the inter-die interconnecting metal layers; and
planarizing a top surface of the second metal layer using a chemical mechanical polishing process.

7. The method of claim 3 , wherein the first mark metal layers include first front-side alignment marks, first front-side overlay marks, second front-side alignment marks, second front-side overlay marks, third front-side alignment marks and third front-side overlay marks.

8. The method of claim 7 , wherein the second metal layer further comprises second mark metal layers including first backside alignment marks, first backside overlay marks, second backside alignment marks, second backside overlay marks, third backside alignment marks and third backside overlay marks;
the first backside alignment marks are matched to the first front-side alignment marks, and the first backside overlay marks are matched to the first front-side overlay marks, in order to enable alignment of the second metal layer with the first metal layer during the exposure using the first photomask module;
the second backside alignment marks are matched to the second front-side alignment marks, and the second backside overlay marks are matched to the second front-side overlay mark, in order to enable alignment of the second metal layer with the first metal layer during the exposure using the second photomask module; and
the third backside alignment marks are matched to the third front-side alignment marks, and the third backside overlay marks are matched to the third front-side overlay marks, in order to enable alignment of the second metal layer with the first metal layer during the exposure using the third photomask module.

9. The method of claim 1 , wherein the second metal layer is any of the second bottom-most to topmost metal layers, which are sequentially stacked from the substrate upward along a thickness direction of the large dies.

10. A large die wafer, comprising a plurality of large dies each having a size greater than a size of a maximum field of exposure of a stepper, each of the large dies comprising:
at least two die portions to be stitched together, each of the die portions comprising a main die region and dummy dicing margins surrounding the main die region, each of the die portions having a size that is smaller than or equal to the size of the maximum field of exposure of the stepper, the die portions each comprising a substrate, a dielectric layer on the substrate and a first metal layer embedded in the dielectric layer, the first metal layer comprising at least to-be-interconnected metal layers for interconnection of the die portions to be stitched together; and
a second metal layer comprising at least inter-die interconnecting metal layers crossing the dummy dicing margins between adjacent die portions and coming into electrical connection with the to-be-interconnected metal layers of the adjacent die portions;
wherein the first metal layer further comprises leading-out metal layers in the main die region, wherein the second metal layer further comprises intra-die metal layers in the main die region, and wherein in each die portion, the intra-die metal layers are electrically connected to the leading-out metal layers along a thickness direction of the die portion, and
wherein the first metal layer further comprises first mark metal layers, the to-be-interconnected metal layers, the

Assignees

• Wuhan Xinxin Semiconductor Mfg

Inventors

• Hu Sheng
• Zhou Jun
• Sun Peng
• Zhan Qiong
• Shi Senhua
• Yang Hu

Classifications

• H10P72/57

  Mask-wafer alignment · CPC title

• H10W46/507

  Located in dummy chips or in reference chips · CPC title

• H10W46/301

  for alignment · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/43

  Layouts of interconnections · CPC title