Method (and related apparatus) that reduces cycle time for forming large field integrated circuits

Patent metadata

Field	Value
Publication number	US-10665455-B2
Application number	US-201816190757-A
Country	US
Kind code	B2
Filing date	Nov 14, 2018
Priority date	Oct 22, 2018
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

First claim

What is claimed is:

1. A method for forming an integrated circuit, the method comprising:
forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion;
patterning the first portion of the first layer, wherein patterning the first portion of the first layer comprises passing radiation through a first reticle to project a first image field over the first portion of the first layer, wherein a first size of the first portion of the first layer corresponds to a second size of the first image field;
patterning the second portion of the first layer, wherein patterning the second portion of the first layer comprises passing radiation through a second reticle to project a second image field over the second portion of the first layer, wherein a third size of the second portion of the first layer corresponds to a fourth size of the second image field;
forming a second layer over the first layer; and
patterning the second layer, where patterning the second layer comprises passing radiation through a third reticle to project a third image field over the second layer, and wherein the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

2. The method of claim 1 , wherein a region of the patterned second layer continuously extends along the first layer from the first portion of the first layer to the second portion of the first layer.

3. The method of claim 1 , wherein the patterned second layer electrically couples a first conductive via disposed beneath an upper surface of the first portion of the first layer to a second conductive via disposed beneath an upper surface of the second portion of the first layer.

4. The method of claim 1 , wherein:
the first image field comprises a first minimum feature size;
the second image field comprises a second minimum feature size; and
the third image field comprises a third minimum feature size, the third minimum feature size being greater than the first minimum feature size and the second minimum feature size.

5. The method of claim 1 , further comprising:
forming an inter-metal dielectric (IMD) layer over the semiconductor wafer, wherein the first layer is formed over the IMD layer.

6. The method of claim 5 , further comprising:
forming a first passivation layer on the IMD layer, wherein the first passivation layer is disposed between the first layer and the IMD layer.

7. The method of claim 6 , wherein the first layer is a second passivation layer that is formed on the first passivation layer.

8. The method of claim 7 , wherein the second layer is formed on the second passivation layer, and wherein patterning the second layer forms a patterned second layer that electrically couples a first conductive via disposed beneath the first portion of the first layer to a second conductive via disposed beneath the second portion of the first layer.

9. The method of claim 8 , wherein forming the first passivation layer comprises:
forming a dielectric layer on an upper surface of the IMD layer, the dielectric layer having a third portion and a fourth portion that are about vertically aligned with the first portion and the second portion of the first layer, respectively;
patterning the third portion of the dielectric layer to form a first via opening in the third portion of the dielectric layer, wherein pattering the third portion comprises passing radiation through a fourth reticle to project a fourth image field over the third portion, wherein a fifth size of the third portion of the dielectric layer corresponds to a sixth size of the fourth image field; and
patterning the fourth portion of the dielectric layer to form a second via opening in the fourth portion of the dielectric layer, wherein patterning the fourth portion comprises passing radiation through a fifth reticle to project a fifth image field over the fourth portion, wherein a seventh size of the fourth portion of the dielectric layer corresponds to an eighth size of the fifth image field.

10. The method of claim 9 , wherein forming the first conductive via and the second conductive via comprises:
forming a conductive layer that fills both the first via opening and the second via opening over the first passivation layer, the conductive layer having a fifth portion and a sixth portion that are about vertically aligned with the third portion and the fourth portion of the dielectric layer, respectively;
patterning the fifth portion of the conductive layer to form the first conductive via, wherein patterning the fifth portion comprises passing radiation through a sixth reticle to project a sixth image field over the fifth portion, wherein a ninth size of the fifth portion of the conductive layer corresponds to a tenth size of the sixth image field; and
patterning the sixth portion of the conductive layer to form the second conductive via, wherein patterning the sixth portion comprises passing radiation through a seventh reticle to project a seventh image field over the sixth portion, wherein an eleventh size of the sixth portion of the conductive layer corresponds to a twelfth size of the seventh image field.

11. A method for forming an integrated circuit, the method comprising:
forming a first integrated circuit unit (ICU) on a first region of a semiconductor wafer by passing radiation through a first reticle to project a first image field toward the first region of the semiconductor wafer, wherein a first size of the first region of the semiconductor wafer corresponds to a maximum image field size of the first reticle;
forming a second ICU on a second region of the semiconductor wafer by passing radiation through a second reticle to project a second image field toward the second region of the semiconductor wafer, wherein a second size of the second region of the semiconductor wafer corresponds to a maximum image field size of the second reticle, and wherein an isolation region separates and electrically isolates the first ICU from the second ICU;
forming a passivation layer over the first ICU, the isolation region, and the second ICU;
forming a conductive layer over the passivation layer; and
patterning the conductive layer, wherein patterning the conductive layer comprises by-passing radiation through a third reticle to project a third image field toward the semiconductor wafer, wherein the third image field covers a majority of the first region and a majority of the second region of the semiconductor wafer.

12. The method of claim 11 , wherein the patterned conductive layer electrically couples the first ICU to the second ICU.

13. The method of claim 12 , wherein:
the first image field defines a minimum feature size of the first ICU;
the second image field defines a minimum feature size of the second ICU; and
the third image field defines a minimum feature size of the patterned conductive layer, wherein the minimum feature size of the patterned conductive layer is greater than both the minimum feature size of the first ICU and the minimum feature size of the second ICU.

14. The method of claim 13 , wherein the minimum feature size of the first ICU is substantially the same as the minimum feature size of the second ICU.

15. The method of claim 14 , wherein the first image field comprises a first pattern of radiation, and the second image field comprises a second pattern of radiation that is substantially the same as the first pattern of radiation.

16. The method of claim 15 , wherein the patterned conductive layer electrically couples the first ICU to the second ICU by bridging a region

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Wen-Chen
• Hsieh Ming-Chang
• Chen Yi-Min

Classifications

• G03F7/70433

  Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors · CPC title

• G03F7/2022

  Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure · CPC title

• G03F1/00

  Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof · CPC title

• G03F7/203 Primary

  comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation · CPC title

• G03F7/70475

  Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display · CPC title