Sense amplifier with read circuit for compute-in-memory

Patent metadata

Field	Value
Publication number	US-12322435-B2
Application number	US-202217692996-A
Country	US
Kind code	B2
Filing date	Mar 11, 2022
Priority date	Jul 23, 2021
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.

First claim

What is claimed is:

1. A memory device, comprising:
a memory array configured to store data;
a sense amplifier circuit coupled to the memory array and having a bit line and an inverted bit line;
a first read circuit connected to one of the bit line and the inverted bit line of the sense amplifier circuit, wherein the first read circuit includes a first input that receives a read column select signal for activating the first read circuit to read the data out of the memory array through the first read circuit during a read operation; and
a load balancing transistor having a gate connected to the other one of the bit line and the inverted bit line and a drain/source path that has each side of the drain/source path connected to a reference,
wherein the other one of the bit line and the inverted bit line is connected to the gate of the load balancing transistor without being connected to a second read circuit and without being connected to another load balancing transistor.

2. The memory device of claim 1 , wherein the sense amplifier circuit includes a second input that receives a write column select signal to write the data into the memory array.

3. The memory device of claim 1 , wherein the first read circuit includes a first transistor having a first gate connected to the one of the bit line and the inverted bit line of the sense amplifier circuit.

4. The memory device of claim 3 , wherein the first transistor includes a first drain/source path and the first read circuit includes a second transistor having a second gate connected to the first input and a second drain/source path connected to the first drain/source path of the first transistor.

5. The memory device of claim 1 , wherein the sense amplifier circuit includes cross-coupled inverters connected to the bit line and the inverted bit line.

6. The memory device of claim 5 , wherein the cross-coupled inverters include two PMOS transistors and two NMOS transistors.

7. The memory device of claim 1 , wherein the memory array is situated one of above the sense amplifier circuit and below the sense amplifier circuit.

8. The memory device of claim 1 , wherein the first read circuit includes one of all NMOS transistors, all PMOS transistors, and a combination of at least one NMOS transistor and at least one PMOS transistor.

9. The memory device of claim 1 , comprising multiple memory MATs, a plurality of sense amplifier circuits, and a plurality of read circuits configured to write data into at least one of the multiple memory MATs and read data from at least one of the multiple memory MATs simultaneously.

10. A memory device, comprising:
a memory array including memory cells;
a sense amplifier having a bit line and an inverted bit line and configured to sense voltages stored in the memory cells and provide corresponding sense amplifier voltages;
a first read circuit connected to one of the bit line and the inverted bit line of the sense amplifier and having a first input that receives a read column select signal for activating the first read circuit to read the sense amplifier voltages and a read port to provide output voltages based on the sense amplifier voltages; and
a load balancing transistor having a gate connected to the other one of the bit line and the inverted bit line and a drain/source path that has each side of the drain/source path connected to a reference,
wherein the other one of the bit line and the inverted bit line is connected to the gate of the load balancing transistor without being connected to a second read circuit and without being connected to another load balancing transistor, and
wherein the first read circuit includes a first transistor having a first drain/source path and a first gate that is connected to the one of the bit line and the inverted bit line of the sense amplifier.

11. The memory device of claim 10 , wherein the sense amplifier includes a second input that receives a write column select signal to write data into the memory cells.

12. The memory device of claim 10 , wherein the first read circuit includes a second transistor having a second gate connected to the first input and a second drain/source path connected to the first drain/source path.

13. The memory device of claim 10 , wherein the sense amplifier includes cross-coupled inverters connected to the bit line and the inverted bit line.

14. The memory device of claim 13 , wherein the cross-coupled inverters include two PMOS transistors and two NMOS transistors.

15. The memory device of claim 10 , comprising:
an analog-to-digital converter that receives the output voltages from the read port and converts the output voltages to digital data, such that compute-in-memory systems use the digital data from the analog-to-digital converter.

16. A method comprising:
providing a memory device that includes a memory array having memory cells and a sense amplifier coupled to the memory array and having a bit line and an inverted bit line;
sensing, using the sense amplifier, voltages stored in the memory cells;
generating sense amplifier voltages that correspond to the voltages sensed by the sense amplifier;
receiving a read column select signal at a read input of a first read circuit that is connected to one of the bit line and the inverted bit line of the sense amplifier to read the sense amplifier voltages with a load balancing transistor having a gate connected to the other one of the bit line and the inverted bit line and a drain/source path that has each side of the drain/source path connected to a reference, the other one of the bit line and the inverted bit line connected to the gate of the single load balancing transistor without being connected to a second read circuit and without being connected to another load balancing transistor;
outputting output voltages from a read port of the first read circuit based on the sense amplifier voltages read by the first read circuit; and
receiving a write column select signal at a write input of the sense amplifier to write data into the memory cells.

17. The method of claim 16 , wherein the first read circuit includes a first transistor having a first gate connected to the one of the bit line and the inverted bit line of the sense amplifier.

18. The method of claim 17 , wherein the first transistor includes a first drain/source path and the first read circuit includes a second transistor having a second gate connected to the first input and a second drain/source path connected to the first drain/source path of the first transistor.

19. The method of claim 16 , wherein sensing, using the sense amplifier, voltages stored in the memory cells includes sensing using cross-coupled inverters.

20. The method of claim 16 , comprising:
receiving the output voltages from the read port at an analog-to-digital converter;
converting the output voltages to digital data; and
using the digital data from the analog-to-digital converter in CIM systems.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Chieh
• Huang Chia-En
• Liu Yi-Ching
• Cheng Wen-Chang
• Wang Yih

Classifications

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C7/1051 Primary

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title