Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10170570-B1
Application number	US-201815909473-A
Country	US
Kind code	B1
Filing date	Mar 1, 2018
Priority date	Sep 21, 2017
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction, and stacked one over the other with an insulating layer disposed between each adjacent electrode;
the plurality of electrodes including a first side, and a second side, each extending in the second direction and spaced from each other in the first direction;
a plurality of protrusion portions extending from the first side of at least two of the electrodes, the protrusion portions spaced from one another in the second direction;
an extraction portion extending from the second side of the electrode on the at least two electrodes having protrusion portions extending from the first side thereof; and
first and second contact plugs extending in a third direction, orthogonal to the first and second directions, one of each contacting the extraction portions connected to one of the two electrodes having protrusion portions extending from the first side thereof,
wherein the extraction portion extending from the uppermost of the two electrodes having protrusion portions extending from the first side thereof is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the two electrodes having protrusion portions extending from the first side thereof.

2. The semiconductor device according to claim 1 , wherein each electrode includes an extraction portion extending from the second side thereof, and the extraction portions extending from the uppermost electrodes, among the plurality of electrodes, are located closer to the center of the second side of the electrode in the second direction than are the extraction portions extending from the lowermost electrodes among the plurality of electrodes.

3. The semiconductor device according to claim 2 , wherein a first portion of the extraction portions extending from the electrodes located between the uppermost and lower most electrodes among the plurality of electrodes extend from the second side of the electrode at a location between the location of the extraction portion on the uppermost electrode among the plurality of electrodes and a first end of the second side of the uppermost electrode in the second direction, and a second portion of the extraction portions among the plurality plurality of electrodes extending from the electrodes located between the uppermost and lowermost electrodes among the plurality of electrodes extend from the second side of the electrode at a location between the location of the extraction portion on the uppermost electrode and a second end of the uppermost electrode in the second direction.

4. The semiconductor device of claim 3 , wherein the number of the first portion of extraction portions and the number of the second portion of the extraction portions is the same.

5. The semiconductor device of claim 3 , wherein there is one more extraction portion in the first portion of extraction portions than in the second portion of extraction portions.

6. The semiconductor device according to claim 2 , wherein at least two insulation layers extend between each two adjacent extraction portions, where one of the two adjacent extraction portions overlies the other of the two adjacent extraction portions in the third direction.

7. The semiconductor device according to claim 2 , wherein the length of the extraction portion in the second direction extending from the second side of any electrode, other than the uppermost electrode or lowermost electrode among among the plurality of electrodes, is greater than the length of the extraction portion in the second direction extending from the second side of the portion immediately thereabove, and smaller than the length of the extraction portion in the second direction extending from the second side of the electrode immediately therebelow.

8. The semiconductor device according to claim 2 , wherein each extraction portion includes a contact region portion where a contact plug extending in the third direction makes contact therewith, and the centers of the contact region portions are evenly spaced form one another in the second direction.

9. The semiconductor device according to claim 8 , wherein the diameter of the contact plug contacting a lower one of the contact region portions of the extraction portions is smaller than the diameter of a contact plug contacting a contact region portion of an extraction portion immediately thereabove.

10. The semiconductor device of claim 2 , further comprising a slit extending through at least one extraction portion, other than the uppermost extraction portion among the plurality of electrodes, at a location intermediate of the opposed ends thereof in the second direction.

11. The semiconductor device according to claim 1 , wherein the extraction portion extending from the second side of the lowermost electrode among the plurality of electrodes extends further in the second direction than does the extraction portion extending from the second side of the uppermost electrode among the plurality of electrodes.

12. The semiconductor device according to claim 1 , wherein the width of the electrode in the first direction is greater than the width of the extraction portions in the first direction.

13. A semiconductor memory device, comprising:
a plurality of first electrodes, extending in a first direction and a second direction orthogonal to the first direction, and stacked one over the other with an insulating layer disposed between each adjacent electrode;
the plurality of electrodes including a first side, and a second side, each extending in the second direction and spaced from each other in the first direction;
a plurality of protruding portions extending in the first direction from the first side of at least two of the electrodes, the protruding portions spaced from one another in the second direction;
an extraction portion extending in the first direction from the second side of each of the electrodes of the plurality of first electrodes together forming a step shaped pattern in the second direction;
a plurality of contact plugs extending in a third direction, orthogonal to the first and second directions, one of each of the contact plugs contacting one of the extraction portions;
a plurality of first memory cells stacked above the semiconductor substrate, each memory cell connected to one of a plurality of first projecting portions stacked one above the other; and
a decoder configured to supply a voltage to the plurality of first electrodes,
wherein, among the extraction portions, a slit extends inwardly of a portion of at least one extraction portion.

14. The semiconductor memory device according to claim 13 , wherein the slit extends in a third direction orthogonal to the first and second directions.

15. The semiconductor memory device according to claim 13 , wherein each extraction portion includes a contact region, and the contact regions extend from the second side of the electrodes by the same length in the first direction.

16. The semiconductor memory device according to claim 13 , wherein each extraction portion includes a contact region, and the different contact regions extend different lengths in the second direction.

17. The semiconductor memory according to claim 16 , wherein the contact plugs are spaced from one another in the first direction, and the distance between each adjacent one of the contacts is the same.

18. The semiconductor memory according

Assignees

• Toshiba Memory Corp

Inventors

• Sonehara Takeshi
• Kodama Erika
• Nakamura Nobutaka
• Inaba Tsuneo
• Nakayama Koichi

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C8/10

  Decoders · CPC title