Apparatuses and methods for performing logical operations using sensing circuitry

Patent metadata

Field	Value
Publication number	US-2018366165-A1
Application number	US-201816111085-A
Country	US
Kind code	A1
Filing date	Aug 23, 2018
Priority date	Oct 29, 2014
Publication date	Dec 20, 2018
Grant date	—

Abstract

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation.

First claim

What is claimed is:

1 . A system, comprising:
a host configured to generate instructions; and a memory device coupled to the host and comprising:
an array of memory cells coupled to sensing circuitry comprising a sense amplifier latch and a compute component latch; and
control circuitry configured to execute instructions from the host by causing logical operations to be performed on operands stored in memory cells corresponding to a same column of the array and coupled to different access lines of the array by:
providing, to logical operation selection logic coupled to the sense amplifier latch and to the compute component latch, a particular combination of logical operation selection signals corresponding to a selected logical operation to be performed on the operands; and

wherein the selected logical operation comprises one from among a group of selectable logical operations corresponding to different respective logical selection signal combinations, the group including an exclusive OR (XOR) logical operation.

2 . The system of claim 1 , wherein the host comprises a processing resource configured to generate the instructions.

3 . The system of claim 2 , wherein the processing resource comprises a host processor.

4 . The system of claim 2 , wherein the processing resource comprises a controller.

5 . The system of claim 1 , wherein the control circuitry comprises a state machine.

6 . The system of claim 1 , wherein the control circuitry comprises a sequencer.

7 . The system of claim 1 , wherein the control circuitry is configured to cause the selected logical operation to be performed without activating a column decode signal corresponding to the same column of the array.

8 . The system of claim 1 , wherein the host comprises a processor, and wherein the processor is on a separate integrated circuit from an integrated circuit on which the memory device is located.

9 . The system of claim 1 , wherein the host and the memory device are on a same integrated circuit.

10 . The system of claim 1 , wherein the host comprises a processing resource configured to perform logical operations in addition to those logical operations performed on the memory device.

11 . The system of claim 1 , further comprising a control bus configured to provide signals from the host to be decoded by the control circuitry.

12 . The system of claim 1 , wherein the operands on which the selected logical operation is performed include:
a first data value stored in a first memory cell coupled to a first access line of the array; and a second data value stored in a second memory cell coupled to a second access line of the array; and wherein the control circuitry configured to cause performance of the selected logical operation by:
activating the first access line a single time; and
activating the second access line a single time.

13 . The system of claim 1 , wherein the group of selectable logical operations further includes an XNOR logical operation, a sense amplifier clear logical operation, and a sense amplifier set logical operation.

14 . A system, comprising:
a host configured to generate instructions; and a memory device coupled to the host and comprising:
an array of memory cells coupled to sensing circuitry comprising a plurality of sense amplifier latches and a respective plurality of compute component latches corresponding thereto on a per column basis; and
control circuitry configured to execute instructions from the host by causing logical operations to be performed, in parallel, on operands stored in memory cells corresponding to a same column of the array and coupled to different access lines of the array by:
providing, to logical operation selection logic, a particular combination of logical operation selection signals corresponding to a selected logical operation to be performed on the operands corresponding to the respective same columns;

wherein the selected logical operation comprises one from among a group of selectable logical operations corresponding to different respective logical selection signal combinations, the group including an exclusive OR (XOR) logical operation, an XNOR logical operation, a sense amplifier reset operation, and a sense amplifier set operation; and wherein the logical operation selection logic comprises a plurality of groups of transistors, with each group being coupled to the compute component latch and the sense amplifier latch of one of the respective columns; and wherein a result of the selected logical operation is obtained without activating a column decode signal.

15 . The system of claim 14 , wherein the memory device comprises a processor-in-memory device coupled to the host via a bus, and wherein the host comprises a processor configured to perform logical operations in addition to logical operations performed on the memory device.

16 . A method, comprising:
generating instructions on a host coupled to a memory device comprising an array of memory cells coupled to sensing circuitry comprising a sense amplifier latch and a compute component latch; and executing the instructions using control circuitry of the memory device, wherein executing the instructions comprises causing performance of logical operations on operands stored in memory cells corresponding to a same column of the array and coupled to different access lines of the array by: providing, to logical operation selection logic coupled to the sense amplifier latch and to the compute component latch, a particular combination of logical operation selection signals corresponding to a selected logical operation to be performed on the operands; and wherein the selected logical operation comprises one from among a group of selectable logical operations corresponding to different respective logical selection signal combinations, the group including an exclusive OR (XOR) logical operation.

17 . The method of claim 16 , further comprising providing the instructions from the host to the control circuitry via a control bus.

18 . The method of claim 16 , wherein the operands on which the selected logical operation is performed include:
a first data value stored in a first memory cell coupled to a first access line of the array; and a second data value stored in a second memory cell coupled to a second access line of the array; and wherein the control circuitry configured to cause performance of the selected logical operation by:
activating the first access line a single time; and
activating the second access line a single time.

19 . The method of claim 18 , wherein performing the selected logical operation includes:
enabling the sense amplifier latch, a first time, while the first access line is activated the single time; subsequently disabling the sense amplifier latch; and subsequently enabling the sense amplifier latch, a second time, while the second access line is activated.

20 . The method of claim 19 , wherein performing the selected logical operation further includes enabling the particular combination of logical operation selection signals corresponding to the selected logical operation while the sense amplifier is enabled the second time.

Assignees

• Micron Technology Inc

Inventors

• Hush Glen E

Classifications

• G11C2207/005

  Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines · CPC title

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title