Digital predistortion for a power amplifier and method therefor

Patent metadata

Field	Value
Publication number	US-9843346-B1
Application number	US-201615222735-A
Country	US
Kind code	B1
Filing date	Jul 28, 2016
Priority date	Jul 28, 2016
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A digital frontend circuit for a radio frequency (RF) comprises a digital predistortion (DPD) block, a plurality of sub-sample delay elements, and a selection circuit. The DPD block for computing predistorted transmit signals according to a Volterra series approximation model. The DPD block has an input for receiving input samples at a first sample rate and an output for providing the predistorted transmit signals at the first sample rate. Each of the sub-sample delay elements provides a delay to an input sample as specified by the Volterra series approximation model, where each of the delays is based on a fraction of the first sample rate. The selection circuit selects one of the plurality of sub-sample delay elements in response to a selection signal from the digital predistortion block. The selection signal for selecting a delay as specified by the Volterra series approximation model.

First claim

What is claimed is:

1. A digital frontend circuit for a radio frequency (RF) transmitter, the digital frontend circuit comprising:
a digital predistortion block for computing predistorted transmit signals according to a Volterra series approximation model, the digital predistortion block having an input for receiving input samples at a first sample rate and an output for providing the predistorted transmit signals at the first sample rate;
a plurality of sub-sample delay elements, each of the sub-sample delay elements for providing a delay to an input sample as specified by the Volterra series approximation model, each of the delays provided by each of the sub-sample delay elements is based on a fraction of the first sample rate; and
a selection circuit coupled to the digital predistortion block and to the plurality of sub-sample delay elements, the selection circuit selecting one of the plurality of sub-sample delay elements in response to a selection signal from the digital predistortion block, the selection signal for selecting a delay as specified by the Volterra series approximation model.

2. The digital frontend circuit of claim 1 , wherein the Volterra series approximation model is computed as

y
⁡

(
n
)

=

∑

{

r
,
q

}

∈
S

⁢

u
⁡

(

n
-

r
/
M

)

⁢

P

r
,
q

⁡

(



u
⁡

(

n
-

q
/
M

)



)

where u(m) represents complex input samples, n is a discrete time, m=n+/−k/M and where k is an integer and k<M, M is an integer, y(n) represents complex pre-distorted output samples, set S is a set of integer delay pairs {r, q}, and polynomial function P r,q ( ) has a distinct order and coefficients for each unique {r,q} pair.

3. The digital frontend circuit of claim 1 , wherein each sub-sample delay element of the plurality of sub-sample delay elements includes a filter.

4. The digital frontend circuit of claim 1 , wherein the digital predistortion block is implemented using a vector processor.

5. The digital frontend circuit of claim 1 , further comprising:
a power amplifier having an input coupled to the output of the digital predistortion block, and an output; and
an adaptation unit having an input coupled to the output of the power amplifier, and an output for providing digital predistortion parameters to the digital predistortion block.

6. The digital frontend circuit of claim 1 further comprising:
a plurality of digital up conversion circuits, each of the plurality of digital up conversion circuits having an input for receiving one of a plurality of samples, each of the plurality of samples having a different sample rate, and an output for providing the plurality of samples at the first sample rate;
a plurality of mixers, each of the plurality of mixers having a first input coupled to a corresponding one of the plurality of digital up conversion circuits, a second input for receiving a sinusoidal signal, and an output;
a combining element having an input coupled to the outputs of each of the plurality of mixers, and an output for providing a composite signal; and
a crest factor reduction circuit having an input coupled to the output of the combining element, and an output coupled to the input of the predistortion block.

7. The digital frontend circuit of claim 1 , wherein the digital frontend circuit is implemented on a single integrated circuit.

8. A digital frontend circuit for a radio frequency (RF) transmitter, the digital frontend circuit comprising:
a digital predistortion block for computing predistorted transmit signals according to a Volterra series approximation model, the digital predistortion block having an input for receiving input samples at a first sample rate and an output for providing the predistorted transmit signals at the first sample rate;
a plurality of sub-sample delay elements, each of the sub-sample delay elements for providing a delay to an input sample as specified by the Volterra series approximation model, each of the delays provided by each of the sub-sample delay elements is based on a fraction of the first sample rate;
a selection circuit coupled to the digital predistortion block and to the plurality of sub-sample delay elements, the selection circuit selecting one of the plurality of sub-sample delay elements in response to a selection signal from the digital predistortion block, the selection signal for selecting a delay as specified by the Volterra series approximation model;
a power amplifier having an input coupled to the output of the digital predistortion block, and an output; and
an adaptation unit having an input coupled to the output of the power amplifier, and an output for providing a tuning signal to the digital predistortion block in response to changes in the output of the power amplifier.

9. The digital frontend circuit of claim 8 , wherein the Volterra series approximation model is computed as

y
⁡

(
n
)

=

∑

{

r
,
q

}

∈
S

⁢

u
⁡

(

n

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Mundarath Jayakrishnan Cheriyath
• Masood Mir
• Rashev Peter Zahariev

Classifications

• H04L27/2614

  Peak power aspects · CPC title

• H03F1/3241

  using predistortion circuits (H03F1/3211, H03F1/3217 take precedence) · CPC title

• H04B2001/0425

  with linearisation using predistortion · CPC title

• H04B1/0475 Primary

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H03F1/32

  Modifications of amplifiers to reduce non-linear distortion (by negative feedback H03F1/34) · CPC title