Diffusion barrier layer on interconnection vias for magnetic tunnel junctions

US12310248B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12310248-B2
Application numberUS-202218148829-A
CountryUS
Kind codeB2
Filing dateDec 30, 2022
Priority dateJun 27, 2018
Publication dateMay 20, 2025
Grant dateMay 20, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: forming a dielectric layer with an opening; depositing a barrier layer in the opening; depositing a conductive layer on the barrier layer; forming a capping layer without performing a vacuum break between depositing the conductive layer and forming the capping layer, wherein forming the capping layer comprises forming the capping layer with a first portion in the conductive layer and surrounded by the barrier layer and a second portion protruding above top surfaces of the barrier layer and the dielectric layer; and forming an electrode on the top surfaces of the barrier layer and the dielectric layer and surrounding the second portion of the capping layer. 2. The method of claim 1 , further comprising depositing an anti-reflective coating on the dielectric layer prior to forming the opening in the dielectric layer. 3. The method of claim 2 , further comprising removing the anti-reflective coating prior to forming the capping layer. 4. The method of claim 1 , wherein depositing the barrier layer comprises depositing a cobalt layer. 5. The method of claim 1 , wherein forming the dielectric layer comprises: depositing a nitride layer; and depositing a low-k dielectric layer on the nitride layer. 6. The method of claim 1 , wherein forming the capping layer comprises forming a cobalt layer or a ruthenium layer. 7. The method of claim 1 , wherein forming the capping layer comprises: depositing a metal precursor layer on the conductive layer; and exposing the metal precursor layer to a plasma comprising argon, hydrogen, nitrogen, or ammonia. 8. The method of claim 1 , wherein forming the capping layer comprises depositing a precursor layer on the conductive layer at a temperature between about 100° C. and about 500° C. 9. The method of claim 1 , further comprising forming a magnetic tunnel junction (MTJ) stack on the electrode. 10. The method of claim 1 , wherein depositing the conductive layer comprises depositing a copper layer or a copper-alloy layer to fill the opening. 11. A method, comprising: forming a dielectric layer on a substrate; forming an opening in the dielectric layer; depositing, in the opening, a metal layer; forming a doped metal nitride layer on the metal layer; depositing a conductive layer on the doped metal nitride layer; and forming a magnetic tunnel junction (MTJ) structure on the metal layer and the doped metal nitride layer. 12. The method of claim 11 , further comprising depositing an anti-reflective coating on the dielectric layer prior to forming the opening. 13. The method of claim 12 , further comprising removing the anti-reflective coating prior to forming the MTJ structure. 14. The method of claim 11 , wherein depositing the conductive layer comprises depositing a copper-free metal. 15. The method of claim 11 , wherein depositing the conductive layer comprises depositing a tungsten layer. 16. The method of claim 11 , wherein forming the doped metal nitride layer comprises doping the metal nitride layer with fluorine, oxygen, nitrogen, chlorine, silicon, carbon, arsenic, germanium, or cobalt dopants. 17. A structure, comprising: an interconnect layer, disposed on a substrate, comprising: a dielectric layer disposed on the substrate, a metal layer disposed in the dielectric layer, a doped metal nitride layer disposed on the metal layer, and a conductive layer disposed on the doped metal nitride layer; and a magnetic tunnel junction (MTJ) structure disposed on the conductive layer. 18. The structure of claim 17 , wherein the conductive layer comprises a copper-free metal. 19. The structure of claim 17 , wherein the doped metal nitride layer comprises fluorine, oxygen, nitrogen, chlorine, silicon, carbon, arsenic, germanium, or cobalt dopants. 20. The structure of claim 17 , wherein the MTJ structure is disposed on the metal layer and the doped metal nitride layer.

Assignees

Inventors

Classifications

  • Barrier, adhesion or liner layers · CPC title

  • by forming openings in the dielectric parts · CPC title

  • covering conductive structures (H10W20/037 takes precedence) · CPC title

  • H10W20/037Primary

    the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

  • of conductive barrier, adhesion or liner layers · CPC title

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What does patent US12310248B2 cover?
The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectiv…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/037. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 20 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).