Integrated circuit devices including vertically stacked field effect transistors

Patent metadata

Field	Value
Publication number	US-12310075-B2
Application number	US-202217720880-A
Country	US
Kind code	B2
Filing date	Apr 14, 2022
Priority date	Sep 9, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

An integrated circuit device includes: an active region extending in a first horizontal direction on a substrate; a first transistor at a first vertical level on the active region, the first transistor including a first source/drain region having a first conductive type; and a second transistor at a second vertical level that is higher than the first vertical level on the active region, the second transistor including a second source/drain region having a second conductive type and overlapping the first source/drain region in a vertical direction, wherein the first source/drain region and the second source/drain region have different sizes.

First claim

What is claimed is:

1. An integrated circuit device comprising:
an active region extending in a first horizontal direction on a substrate;
a gate line extending in a second horizontal direction on the active region, wherein the gate line has a first side and a second side that is opposite to the first side in the first horizontal direction;
a first transistor at a first vertical level on the active region, the first transistor comprising a first source/drain region having a first conductive type on the first side of the gate line; and
a second transistor at a second vertical level that is higher than the first vertical level on the active region, the second transistor comprising a second source/drain region having a second conductive type on the first side of the gate line and overlapping the first source/drain region in a vertical direction,
wherein a maximum width of the first source/drain region in the first horizontal direction is less than a maximum width of the second source/drain region in the first horizontal direction, and
wherein the first horizontal direction intersects the second horizontal direction.

2. The integrated circuit device of claim 1 , wherein a size of the second source/drain region is greater than a size of the first source/drain region.

3. The integrated circuit device of claim 1 , wherein:
the first transistor further comprises a first nano-sheet on the active region and contacting the first source/drain region, and a first sub gate portion of the gate line surrounding the first nano-sheet,
the second transistor further comprises a second nano-sheet apart from the active region in the vertical direction with the first nano-sheet between the second nano-sheet and the active region, the second nano-sheet contacting the second source/drain region, and a second sub gate portion of the gate line connected to the first sub gate portion of the gate line as one body and surrounding the second nano-sheet, and
a maximum width of the second nano-sheet is less than a maximum width of the first nano-sheet in the first horizontal direction.

4. The integrated circuit device of claim 1 ,
wherein the gate line is shared by the first transistor and the second transistor.

5. The integrated circuit device of claim 1 , further comprising:
a first nano-sheet on the active region and contacting the first source/drain region; and
a second nano-sheet overlapping the first nano-sheet in the vertical direction and contacting the second source/drain region,
wherein the gate line surrounds the first nano-sheet and the second nano-sheet, wherein the gate line comprises:
a first sub gate portion facing the first source/drain region in the first horizontal direction and at least partially covering the first nano-sheet;
a second sub gate portion facing the second source/drain region in the first horizontal direction and at least partially covering the second nano-sheet; and
a main gate portion connected to the first sub gate portion and the second sub gate portion as one body and at least partially covering a top surface of the second nano-sheet, and
a maximum width of the second sub gate portion is less than a maximum width of the first sub gate portion in the first horizontal direction.

6. The integrated circuit device of claim 1 , wherein the first source/drain region comprises a first semiconductor layer doped with an n-type dopant, and
the second source/drain region comprises a second semiconductor layer doped with a p-type dopant.

7. The integrated circuit device of claim 1 , further comprising an insulation pattern between the first source/drain region and the second source/drain region,
wherein the first source/drain region and the second source/drain region are apart from each other with the insulation pattern therebetween in the vertical direction.

8. The integrated circuit device of claim 1 , further comprising:
a first nano-sheet on the active region and contacting the first source/drain region; and
a second nano-sheet overlapping the first nano-sheet in the vertical direction and contacting the second source/drain region,
wherein the gate line comprises a first sub gate portion surrounding the first nano-sheet and a second sub gate portion surrounding the second nano-sheet, and
wherein:
the first source/drain region comprises a first protrusion portion protruding toward the first sub gate portion to overlap a portion of the first nano-sheet in the vertical direction, and
the second source/drain region comprises a second protrusion portion protruding toward the second sub gate portion to overlap a portion of the second nano-sheet in the vertical direction.

9. An integrated circuit device comprising:
a fin-type active region protruding in a vertical direction from a substrate and extending in a first horizontal direction;
at least one first nano-sheet at a first separation distance in the vertical direction from a top of the fin-type active region;
a plurality of first source/drain regions at both sides of the at least one first nano-sheet, the plurality of first source/drain regions each comprising a first semiconductor material having a first conductive type;
at least one second nano-sheet at a second separation distance that is greater than the first separation distance in the vertical direction from the top of the fin-type active region and overlapping the at least one first nano-sheet in the vertical direction;
a plurality of second source/drain regions at both sides of the at least one second nano-sheet and overlapping the plurality of first source/drain regions in the vertical direction, each of the plurality of second source/drain regions comprising a second semiconductor material having a second conductive type; and
a gate line surrounding the at least one first nano-sheet and the at least one second nano-sheet,
wherein a maximum width of each of the plurality of first source/drain regions in the first horizontal direction differs from a maximum width of each of the plurality of second source/drain regions in the first horizontal direction.

10. The integrated circuit device of claim 9 , wherein each of the plurality of first source/drain regions comprise a first semiconductor layer doped with an n-type dopant,
each of the plurality of second source/drain regions comprise a second semiconductor layer doped with a p-type dopant, and
the maximum width of each of the plurality of second source/drain regions is greater than the maximum width of each of the plurality of first source/drain regions.

11. The integrated circuit device of claim 10 , wherein
a size of each of the plurality of second source/drain regions is greater than a size of each of the plurality of first source/drain regions.

12. The integrated circuit device of claim 9 , wherein the at least one first nano-sheet comprises two first nano-sheets adjacent to each other,
the at least one second nano-sheet comprises two second nano-sheets adjacent to each other,
the gate line comprises a first sub gate portion between the two first nano-sheets and a second sub gate portion between the two second nano-sheets, and
a maximum width of the second sub gate portion is less than a maximum width of the first sub gate portion in the first horizontal direction.

13. The integrated circuit device of claim 9 , wherein the at least one first nano-sheet comprises two first nano-sheets adjacent to each other,
the at least one second nano-sheet comprises two second nano-sheets adjacent to each other, and
a separation distance between the at least one first nano-sheet and the at least one second nano-sheet in the vertical direction is greater than a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dohee
• Jang Sunguk
• Kuh Bongjin
• Lee Kongsoo
• Hong Sahwan

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title