Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor

Patent metadata

Field	Value
Publication number	US-9875945-B2
Application number	US-201715457492-A
Country	US
Kind code	B2
Filing date	Mar 13, 2017
Priority date	Apr 15, 2016
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.

First claim

What is claimed is:

1. A method of forming an electrical device comprising:
forming at least one first fin structure in a lateral device region of a substrate and forming at least one second fin structure in a vertical device region of the substrate;
forming a drift region in the lateral device region and a dopant region in the vertical device region of the substrate for a source region or drain region in the vertical device region;
forming a dielectric layer in the lateral device region of the substrate and the vertical device region of the substrate, wherein a first portion of the dielectric layer provides a drift region gate dielectric for an LDMOS device being formed in the lateral device region, and a second portion of the dielectric layer provides a spacer for the VFET being formed in the vertical device region;
forming a gate structure for the LDMOS device and the VFET device; and
forming an epitaxial semiconductor material on the at least one first fin structure in the lateral device region of the substrate and the at least one second fin structure in the vertical device region.

2. The method of claim 1 , wherein the epitaxial semiconductor material in the lateral device region provides a dopant region for one of source region or drain region for the LDMOS device.

3. The method of claim 1 , wherein the epitaxial semiconductor material in the vertical device region provides a doped region that provides a source region or drain region opposite the source region or drain region provided by the dopant region formed simultaneously with the drift region.

4. The method of claim 1 , wherein the substrate is a bulk semiconductor substrate.

5. The method claim 1 , wherein the VFET further comprises:
a vertical channel region positioned within the second fin structure;

the gate structure present on the vertical channel region, the gate structure including at least one VFET gate dielectric and at least one VFET gate conductor; and
a second spacer present between an upper surface of the gate structure and the epitaxial semiconductor material in the vertical device region.

6. The method of claim 5 , wherein the LDMOS comprises:
a fin gate dielectric present on the first fin structure;
an LDMOS gate structure present on the drift region gate dielectric and the fin gate dielectric; and
a first epitaxial semiconductor material formed on an upper surface of said first fin structure.

7. The method of claim 6 , wherein the drift region gate dielectric is on a same level as the dielectric layer that provides the spacer for the VFET.

8. The method of claim 7 , wherein the drift region gate dielectric has multiple thickness regions.

9. The method of claim 1 further comprising forming an opening through the drift region gate dielectric and forming a contact to the drift region.

10. A method of forming an electrical device comprising:
forming at least one first fin structure in a lateral device region of a substrate and forming at least one second fin structure in a vertical device region of the substrate;
forming a drift region in the lateral device region and a dopant region in the vertical device region of the substrate for a source region or drain region in the vertical device region; and
forming a dielectric layer in the lateral device region of the substrate and the vertical device region of the substrate, wherein a first portion of the dielectric layer provides a drift region gate dielectric for an LDMOS device being formed in the lateral device region, and a second portion of the dielectric layer provides a spacer for the VFET being formed in the vertical device region.

11. The method of claim 10 , wherein an epitaxial semiconductor material that is formed on the at least one fin structure in the lateral device region provides a dopant region for one of source region or drain region for the LDMOS device.

12. The method of claim 11 , wherein an epitaxial semiconductor material that is formed on the at least one second fin structure in the vertical device region provides a doped region that provides a source region or drain region opposite the source region or drain region provided by the dopant region formed simultaneously with the drift region.

13. The method of claim 10 , wherein the substrate is a bulk semiconductor substrate.

14. The method claim 12 , wherein the VFET further comprises:
a vertical channel region positioned within the second fin structure;
a gate structure present on the vertical channel region, the gate structure including at least one VFET gate dielectric and at least one VFET gate conductor; and
a second spacer present between an upper surface of the gate structure and the epitaxial semiconductor material in the vertical device region.

15. The method of claim 14 , wherein the LDMOS comprises:
a fin gate dielectric present on the first fin structure;
an LDMOS gate structure present on the drift region gate dielectric and the fin gate dielectric; and
said epitaxial semiconductor material formed on an upper surface of said first fin structure.

16. The method of claim 15 , wherein the drift region gate dielectric is on a same level as the dielectric layer that provides the spacer first VFET.

17. The method of claim 16 , wherein the drift region gate dielectric has multiple thickness regions.

18. The method of claim 10 further comprising forming an opening through the drift region gate dielectric and forming a contact to the drift region.

19. The method of claim 10 , wherein the VFET is an n-type device.

20. The method of claim 10 , wherein the VFET is a p-type device.

Assignees

• IBM

Inventors

• Anderson Brent A
• Loiseau Alain

Classifications

• H01L21/823821

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L21/823871

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic