Vertical field effect transistor (VFET) programmable complementary metal oxide semiconductor inverter

Patent metadata

Field	Value
Publication number	US-10388648-B2
Application number	US-201916298458-A
Country	US
Kind code	B2
Filing date	Mar 11, 2019
Priority date	Nov 21, 2017
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.

First claim

The invention claimed is:

1. A semiconductor inverter comprising:
a first vertical semiconductor device including a first channel region present in a first fin structure having source and drain regions of a first conductivity type;
a second vertical semiconductor device including a second channel region present in a second fin structure having source and drain regions of a second conductivity type; and
a common contact electrically connecting an upper source and drain region of the first conductivity type for the first vertical semiconductor device to an upper source and drain region of the second conductivity type for the second vertical semiconductor device, the common electrical contact providing an output for the inverter, the common contact provided by a metal fill formed in a trench, a first end of metal fill contacting the upper source and drain region for the first vertical semiconductor device, and a second end of the metal fill contacting the upper source and drain region of the second vertical semiconductor device.

2. The semiconductor inverter of claim 1 , wherein the first vertical semiconductor device is in a first region of a supporting substrate, and the second vertical semiconductor device is present in a second region of the supporting substrate.

3. The semiconductor inverter of claim 2 , wherein the first region of the supporting substrate is separated from a second region of the supporting substrate by an isolation region.

4. The semiconductor inverter of claim 1 , wherein a negative supply voltage (VSS) connection is in electrical communication with one of source and drain regions of the first conductivity type or source and drain regions of the second conductivity type that is not directly contacted by the common contact.

5. The semiconductor inverter of claim 3 , wherein the first vertical semiconductor device includes a first source and drain region of a first conductivity type on the supporting substrate, the first fin structure atop the first source and drain region having the first conductivity type, and a second source and drain region of a first conductivity type comprised of epitaxial semiconductor material present on an end of the first fin structure that is opposite and end of the first fin structure directly contacting the first source and drain region having the first conductivity type.

6. The semiconductor inverter of claim 5 , wherein the first conductivity type is n-type.

7. The semiconductor inverter of claim 1 , wherein a positive supply voltage (VDD) connection is in electrical communication with one of the first conductivity type source and drain regions or the second conductivity type source and drain regions that is not directly contacted by the common contact.

8. The semiconductor inverter of claim 3 , wherein the second vertical semiconductor device includes a first source and drain region of a second conductivity type on the supporting substrate, the second fin structure atop the first source and drain region having the second conductivity type, and a second source and drain region of a second conductivity type comprised of epitaxial semiconductor material present on an end of the second fin structure that is opposite an end of the second fin structure directly contacting the first source and drain region having the second conductivity type.

9. The semiconductor inverter of claim 1 , wherein the first fin structure and the second fin structure are separated by a pitch ranging from 25 nm to 40 nm.

10. A semiconductor inverter comprising:
a first vertical semiconductor device having source and drain regions of a first conductivity type;
a second vertical semiconductor device having source and drain regions of a second conductivity type; and
a common contact electrically connecting an upper source and drain region of the first conductivity type for the first vertical semiconductor device to an upper source and drain region of the second conductivity type for the second vertical semiconductor device, the common electrical contact providing an output for the inverter, the common contact provided by a metal, a first end of the metal contacting the upper source and drain region for the first vertical semiconductor device, and a second end of the metal contacting the upper source and drain region of the second vertical semiconductor device.

11. A method of forming a semiconductor inverter comprising:
forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate;
forming a second conductivity type vertically orientated semiconductor device in a second region of the substrate; and
forming a common contact electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device, the common electrical contact providing an output for the inverter, the common contact provided by a metal, a first end of metal contacting the upper source and drain region for the first vertical semiconductor device, and a second end of the metal contacting the upper source and drain region of the second vertical semiconductor device.

12. The method of claim 11 , wherein a first channel for the first conductivity type vertically orientated semiconductor device is present within a first fin structure.

13. The method of claim 12 , wherein the first fin structure is epitaxially formed.

14. The method of claim 12 , wherein a second channel for the second conductivity type vertically orientated semiconductor device is present in a second fin structure.

15. The method of claim 14 , wherein the second fin structure is epitaxially formed.

16. The method of claim 14 , wherein the first fin structure and the second fin structure are separated by a pitch ranging from 25 nm to 40 nm.

17. The method of claim 16 , wherein the second gate structure that provides the floating gate includes a gate dielectric having a greater thickness than the gate dielectric in the first gate structure.

18. The method of claim 15 , wherein the upper source and drain region for the first conductivity type vertically orientated semiconductor device, and the upper source and drain region of the second conductivity type vertically orientated semiconductor device are epitaxially formed.

19. The method of claim 15 , wherein a negative supply voltage (VSS) connection is formed in electrical communication with one of source and drain regions of one of said first and second conductivity type vertically orientated semiconductor device.

20. The method of claim 15 , wherein a positive supply voltage (VDD) connection is formed in electrical communication with one of source and drain regions of one of said first and second conductivity type vertically orientated semiconductor device.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Hashemi Pouya
• Ning Tak H
• Reznicek Alexander

Classifications

• H01L27/0617 Primary

  Electricity · mapped topic

• H01L29/7889

  Electricity · mapped topic

• H01L21/82385

  Electricity · mapped topic

• H01L29/42364

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic