Packaging architecture for disaggregated integrated voltage regulators

Patent metadata

Field	Value
Publication number	US-12308362-B2
Application number	US-202117412810-A
Country	US
Kind code	B2
Filing date	Aug 26, 2021
Priority date	Aug 26, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

First claim

The invention claimed is:

1. A microelectronic assembly, comprising:
a first integrated circuit (IC) die having an electrical load circuit;
a second IC die having a portion of a voltage regulator (VR), wherein:
the second IC die has a first side facing the first IC die and a second side opposite the first side,
the first side comprises first conductive contacts, and
the second side comprises second conductive contacts; and

a third IC die comprising inductors of the VR; wherein:
the third IC die is between the first IC die and the second IC die,
the third IC die has a third side facing the second IC die and a fourth side facing the first IC die,
the third side comprises third conductive contacts coupled with the second conductive contacts,
the fourth side comprises fourth conductive contacts coupled with fifth conductive contacts of the first IC die, and
the VR is configured to receive power at a first voltage and to provide power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage.

2. The microelectronic assembly of claim 1 , wherein the inductors in the third IC die comprise magnetic thin films.

3. The microelectronic assembly of claim 1 , further comprising:
a package substrate having conductive pathways, wherein:
the second IC die is between the third IC die and the package substrate,
the package substrate comprises sixth conductive contacts, and
the first conductive contacts on the first side of the second IC die are coupled with the sixth conductive contacts.

4. The microelectronic assembly of claim 3 , further comprising a mold compound between the first IC die and the package substrate, wherein the second IC die and the third IC die are in the mold compound.

5. The microelectronic assembly of claim 4 , further comprising through-dielectric vias (TDVs) in the mold compound and coplanar with the second IC die.

6. The microelectronic assembly of claim 3 , wherein:
the first IC die is electrically coupled to the package substrate with a first plurality of interconnects,
the second IC die is electrically coupled to the package substrate with a second plurality of interconnects, and
the first plurality of interconnects and the second plurality of interconnects are of different types.

7. The microelectronic assembly of claim 1 , wherein the third IC die is similarly sized as the second IC die, and the first IC die further comprises decoupling metal-insulator-metal (MIM) capacitors.

8. The microelectronic assembly of claim 1 , wherein the third IC die is similarly sized as the first IC die, and the third IC die further comprises decoupling MIM capacitors.

9. The microelectronic assembly of claim 1 , wherein the inductors are stacked within the third IC die.

10. The microelectronic assembly of claim 1 , wherein the portion of the VR in the second IC die includes power train and drivers, and another portion of the VR comprising a controller is in the first IC die.

11. The microelectronic assembly of claim 1 , further comprising a stacked arrangement of multiple ones of the microelectronic assembly, wherein at least some of the first IC dies in the stacked arrangement comprise through-silicon vias (TSVs).

12. The microelectronic assembly of claim 1 , wherein the second IC die further comprises TSVs electrically coupling two opposing faces of the second IC die.

13. The microelectronic assembly of claim 1 , further comprising:
a mold compound at least partially around the second die and the third die.

14. An integrated circuit (IC), comprising:
an electrical load circuit in a first IC die;
a portion of a voltage regulator (VR) in a second IC die; and
inductors in a third IC die, wherein:
the third die has a first side coupled with the first IC die and a second side coupled with the second IC die,
a mold compound is at least partially surrounding the second die and the third die, and
the VR is configured to receive power at a first voltage and to provide power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage.

15. The IC of claim 14 , wherein the third IC die is between the first IC die and the second IC die.

16. The IC of claim 14 , wherein:
the second IC die and the third IC die are comprised in an interposer,
the interposer comprises the mold compound and a through-dielectric via (TDV) in the mold compound between the first IC die and a package substrate, and
the TDV is coplanar with the second IC die and the third IC die.

17. The IC of claim 14 , wherein:
the first side comprises first conductive contacts coupled with first corresponding conductive contacts of the first IC die, and
the second side comprises second conductive contacts coupled with second corresponding conductive contacts of the second die.

18. A method comprising:
providing a first IC die with an electrical load circuit;
providing a second IC die with a portion of a voltage regulator (VR);
providing a third IC die with inductors; and
electrically coupling the first IC die, the second IC die and the third IC die to generate the VR, wherein the VR is configured to convert power received at a first voltage into power delivered at a second voltage to the electrical load circuit, the first voltage being higher than the second voltage, and wherein:
the third IC die has a first face comprising first conductive contacts and a second face comprising second conductive contacts, and
electrically coupling the first IC die, the second IC die, and the third IC die comprises coupling the first conductive contacts with first corresponding conductive contacts of the first IC die and coupling the second conductive contacts with second corresponding conductive contacts of the second die.

19. The method of claim 18 , further comprising providing another portion of the VR in the first IC die, wherein the portion of the VR in the second IC die is configured to operate at the first voltage, and the another portion is configured to operate at the second voltage.

20. The method of claim 18 , further comprising assembling a stack of microelectronic assemblies one on top of another, each microelectronic assembly comprising the third IC die between the first IC die and the second IC die.

Assignees

• Intel Corp

Inventors

• Radhakrishnan Kaladhar
• Bharath Krishna
• Lambert William J
• Elsherbini Adel A
• Srinivasan Sriram
• Schaef Christopher

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W44/226

  for HF amplifiers · CPC title

• H10W44/212

  Coaxial feed-throughs in substrates · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title