Microelectronic assemblies having an integrated voltage regulator chiplet

Patent metadata

Field	Value
Publication number	US-2020105653-A1
Application number	US-201816145059-A
Country	US
Kind code	A1
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.

First claim

1 . A microelectronic assembly, comprising:
a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes:
a capacitor at the first surface; and
an element at the second surface, wherein the element includes a switching transistor or a diode.

2 . The microelectronic assembly of claim 1 , the package substrate further includes a power plane, and wherein the capacitor is electrically coupled to the power plane in the package substrate.

3 . The microelectronic assembly of claim 1 , wherein the capacitor is a metal-insulator-metal (MIM) capacitor.

4 . The microelectronic assembly of claim 3 , wherein the MIM capacitor is a multi-layer capacitor.

5 . The microelectronic assembly of claim 1 , wherein the first surface of the die is coupled to the surface of the package substrate by first interconnects, the package substrate further includes an inductor, and the element is coupled to the inductor in the package substrate via the first interconnects.

6 . The microelectronic assembly of claim 1 , wherein the die is a central processing unit, a graphics processing unit, a digital signal processor, an application specific integrated circuit, a server processor, or a crypto processor.

7 . The microelectronic assembly of claim 1 , wherein the die includes a core, and wherein the chiplet is electrically coupled to the core.

8 . The microelectronic assembly of claim 1 , wherein the die includes a first core and a second core, and wherein the chiplet is electrically coupled to the first core and the second core.

9 . A microelectronic assembly, comprising:
a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet, having a first surface and an opposing second surface, between the package substrate and the die, wherein the chiplet includes:
an element at the first surface, wherein the element is coupled to the surface of the package substrate via first interconnects, and wherein the element includes a switching transistor or a diode; and
a metal-insulator-metal (MIM) capacitor at the second surface, wherein the MIM capacitor is coupled to the first surface of the die via second interconnects.

10 . The microelectronic assembly of claim 9 , wherein the package substrate includes a power plane and a ground plane, and wherein the element is electrically coupled to the power plane and to the ground plane via conductive pathways in the package substrate.

11 . The microelectronic assembly of claim 9 , wherein the package substrate includes an inductor, and wherein the element is coupled to the inductor via a conductive pathway in the package substrate.

12 . The microelectronic assembly of claim 9 , wherein the die includes: a control circuit.

13 . The microelectronic assembly of claim 9 , wherein the first surface of the chiplet further includes: a MIM capacitor.

14 . An integrated voltage regulator (IVR) chiplet, comprising:
an active layer, having a first surface and an opposing second surface, wherein the active layer includes a first switching transistor and a second switching transistor; and a backside layer on the second surface of the active layer, wherein the backside layer includes a capacitor.

15 . The IVR chiplet of claim 14 , wherein the capacitor is a metal-insulator-metal (MIM) capacitor.

16 . The IVR chiplet of claim 15 , wherein the MIM capacitor includes a high-k dielectric material.

17 . The IVR chiplet of claim 14 , further including: a control circuit.

18 . The IVR chiplet of claim 14 , wherein the first switching transistor is a p-type metal oxide semiconductor transistor, and wherein the second switching transistor is an n-type metal oxide semiconductor transistor.

19 . The IVR chiplet of claim 14 , further including: an inductor.

20 . The IVR chiplet of claim 19 , wherein the inductor is a thin film magnetic core inductor.

21 . A method of manufacturing an IVR chiplet, comprising:
removing a material from a backside surface of a die, wherein the die has an active surface and the backside surface that is opposite the active surface; forming a capacitor on a backside surface of a die; forming a first conductive pathway from the backside surface of the die to a first plate of the capacitor; and forming a second conductive pathway from the backside surface of the die to a second conductive plate of the capacitor.

22 . The method of claim 21 , wherein forming the capacitor includes:
forming a first conductive layer; forming and patterning a dielectric layer on the first conductive layer; and forming a second conductive layer on the dielectric layer.

23 . The method of claim 22 , wherein the dielectric layer includes a high-k dielectric material.

24 . The method of claim 22 , wherein the first conductive layer or the second conductive layer includes copper.

25 . The method of claim 21 , wherein the die includes gallium nitride, gallium arsenide, indium phosphide, silicon, or germanium.

Assignees

• Intel Corp

Inventors

• Elsherbini Adel A
• Radhakrishnan Kaladhar
• Bharath Krishna
• Liff Shawna M
• Swan Johanna M

Classifications

• G05F1/46 Primary

  wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) · CPC title

• H01F27/24

  Magnetic cores · CPC title

• H01L28/10

  Electricity · mapped topic

• H01L28/40

  Electricity · mapped topic

• H01L24/17

  Electricity · mapped topic