Integrating and accessing passive components in wafer-level packages

Patent metadata

Field	Value
Publication number	US-12308335-B2
Application number	US-202318128077-A
Country	US
Kind code	B2
Filing date	Mar 29, 2023
Priority date	Sep 29, 2017
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.

First claim

The invention claimed is:

1. A device, comprising:
a passive device in a package, the passive device having a top side above a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall laterally opposite the second sidewall;
first and second vias in the package and adjacent to the first sidewall of the passive device; and
third and fourth vias in the package and adjacent to the second sidewall of the passive device;
a first redistribution layer over the top side of the passive device, over the first via, over the second via, over the third via and over the fourth via, wherein the passive device is directly connected to the first redistribution layer;
a first die over the first redistribution layer, the first die vertically overlapping with the first via, the second via, and the passive device;
a second die over the first redistribution layer, the second die vertically overlapping with the third via and the fourth via;
a mold compound laterally between and in contact with the first die and the second die;
a second redistribution layer below the bottom side of the passive device, below the first via, below the second via, below the third via and below the fourth via;
a second passive device laterally adjacent to the first sidewall of the passive device; and
a third passive device laterally adjacent to the second sidewall of the passive device.

2. The device of claim 1 , further comprising:
solder balls below the second redistribution layer.

3. The device of claim 1 , wherein the package comprises an encapsulant in contact with the first sidewall and the second sidewall of the passive device.

4. The device of claim 1 , wherein the mold compound is in contact with a side of the first die laterally opposite the second die, and wherein the mold compound is in contact with a side of the second die laterally opposite the first die.

5. The device of claim 1 , wherein the passive device is a surface-mounted passive device.

6. A device, comprising:
an upper package comprising a first die laterally spaced apart from a second die by a mold compound, and a redistribution layer beneath the first die and the second die and the mold compound; and
a lower package, wherein the redistribution layer of the upper package is coupled to the lower package by solder balls, wherein the lower package comprises passive devices, and vias adjacent to the passive devices, and wherein a first one of the passive devices is directly connected to the redistribution layer of the upper package, wherein a second one of the passive devices is laterally adjacent to a first sidewall of the first one of the passive devices, and wherein a third one of the passive devices is laterally adjacent to a second sidewall of the first one of the passive devices, the second sidewall opposite the first sidewall.

7. The device of claim 6 , wherein the lower package further comprises a second redistribution layer beneath the passive devices and the vias.

8. The device of claim 7 , further comprising:
second solder balls below the second redistribution layer.

9. The device of claim 6 , wherein the lower package further comprises an encapsulant in contact with sidewalls of the passive devices.

10. The device of claim 9 , wherein the vias extend through the encapsulant.

11. The device of claim 6 , wherein the lower package further comprises a die beneath one or more of the passive devices.

12. The device of claim 6 , wherein the first one of the passive devices is vertically beneath the first die.

13. The device of claim 12 , wherein the first one of the passive devices is not vertically beneath the second die.

14. The device of claim 13 , wherein a second one of the passive devices is vertically beneath the second die and is not vertically beneath the first die.

15. A device, comprising:
a passive device in a package, the passive device having a top side above a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall laterally opposite the second sidewall;
first and second vias in the package and adjacent to the first sidewall of the passive device; and
third and fourth vias in the package and adjacent to the second sidewall of the passive device;
a first redistribution layer over the top side of the passive device, over the first via, over the second via, over the third via and over the fourth via;
a first die over the first redistribution layer, the first die vertically overlapping with the first via, the second via, and the passive device;
a second die over the first redistribution layer, the second die vertically overlapping with the third via and the fourth via;
a mold compound laterally between and in contact with the first die and the second die;
a second redistribution layer below the bottom side of the passive device, below the first via, below the second via, below the third via and below the fourth via;
a second passive device laterally adjacent to the first sidewall of the passive device; and
a third passive device laterally adjacent to the second sidewall of the passive device.

Assignees

• Intel Corp

Inventors

• Signorini Gianni
• Sciriha Veronica
• Wagner Thomas

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title