Semiconductor device package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12308306-B2
Application number	US-202318201145-A
Country	US
Kind code	B2
Filing date	May 23, 2023
Priority date	Jan 22, 2020
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S 11 parameter of the connector is less than −20 dB.

First claim

What is claimed is:

1. A semiconductor device package, comprising:
a carrier;
a first electronic component disposed adjacent to the carrier;
a connector disposed adjacent to the carrier and electrically connected to the first electronic component through the carrier, the connector including a first group of conductive posts adjacent to the first electronic component and a second group of conductive posts farther away from the first electronic component than the first group of conductive posts;
a first package body covering the first electronic component and exposing a portion of the connector; and
a shielding layer covering the first package body and exposing the portion of the connector, wherein a lower surface of the shielding layer and a bottom surface of the carrier are substantially coplanar,
wherein the top surface of the connector is higher than a top surface of the first electronic component, and
wherein, in a unit area, an arrangement of the first group of conductive posts is more dense than an arrangement of the second group of conductive posts.

2. The semiconductor device package of claim 1 , wherein the shielding layer includes a first portion covering a top surface of the first package body and a second portion covering a lateral surface of the first package body, wherein a thickness of the first portion of the shielding layer is greater than a thickness of the second portion of the shielding layer, and wherein the second group of conductive posts is disposed more adjacent to the second portion of the shielding layer than the first group of conductive posts.

3. The semiconductor device package of claim 1 , further comprising a second electronic component disposed adjacent to the carrier and covered by the first package body, wherein the first electronic component is an active component and the second electronic component is a passive component, the first electronic component is disposed between the second electronic component and the connector, and wherein the first electronic component is closer to the second electronic component than to the connector.

4. The semiconductor device package of claim 1 , wherein a number of columns of the first group of conductive posts is greater than a number of columns of the second group of conductive posts.

5. The semiconductor device package of claim 1 , further comprising a second electronic component disposed adjacent to the carrier, wherein the first electronic component and the second electronic component are encapsulated by the first package body, and the first package body is in contact with the shielding layer.

6. The semiconductor device package of claim 1 , further comprising a group of common ground posts disposed between the first group of conductive posts and the second group of conductive posts to separate the first group of conductive posts and the second group of conductive posts.

7. The semiconductor device package of claim 6 , wherein the first group of conductive posts, the second group of conductive posts, and the group of common ground posts are encapsulated by a second package body, and the second package body is encapsulated by the first package body.

8. The semiconductor device package of claim 1 , wherein the first group of conductive posts is disposed between the second group of conductive posts and the first electronic component.

9. The semiconductor device package of claim 1 , wherein the shielding layer is in contact with a ground post of the connector.

10. A semiconductor device package, comprising:
a carrier;
an electronic component disposed adjacent to the carrier;
a connector disposed over the carrier and electrically connected to the electronic component through the carrier;
a first package body covering the connector and the electronic component; and
a shielding layer covering the first package body, wherein the second group of conductive posts is disposed more adjacent to the first group of conductive posts than the electronic component, and wherein the first group of conductive posts and the second group of conductive posts are exposed from the shielding layer,
wherein a first portion of the first package body is disposed between a bottom surface of the connector and a top surface of the carrier,
wherein the connector has a first group of conductive posts and a second group of conductive posts, and a pitch of two adjacent conductive posts of the first group of conductive posts is different from a pitch of two adjacent conductive posts of the second group of conductive posts.

11. The semiconductor device package of claim 10 , further comprising a second package body encapsulating the connector to constitute a connector module and a shielding layer in contact with a top surface of the first package body and a top surface of the second package body.

12. The semiconductor device package of claim 11 , wherein a width of the connector module is greater than a width of the electronic component.

13. The semiconductor device package of claim 11 , wherein the top surface of the second package body and the top surface of a conductive post of the first group of conductive posts are substantially coplanar.

14. The semiconductor device package of claim 10 , wherein the shielding layer is in contact with a conductive via, wherein the conductive via is configured to function as a compartment shielding to provide electromagnetic interference (EMI) shielding for the electronic component and the connector.

15. The semiconductor device package of claim 14 , wherein a height of the conductive via is substantially the same as a thickness of the first package body.

16. The semiconductor device package of claim 14 , wherein the conductive via is encapsulated by the first package body.

17. The semiconductor device package of claim 14 , wherein the conductive via is disposed between the electronic component and the first group of conductive posts of the connector.

18. The semiconductor device package of claim 10 , further comprising a second package body encapsulating the connector to constitute a connector module, wherein an area of the connector module is greater than an area of the electronic component from a top view perspective.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yu Yuanhao
• Chen cheng yuan
• Chen Chun Chen
• Li Jiming
• Tu Chien-Wen

Classifications

• H10W44/203

  Electrical connections · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W42/273

  the arrangements being between laterally adjacent chips, e.g. walls between chips · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title