Three-dimensional memory and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12302559-B2
Application number	US-202217582871-A
Country	US
Kind code	B2
Filing date	Jan 24, 2022
Priority date	Nov 25, 2020
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

The present disclosure relates to a three-dimensional memory and a method for manufacturing the same. The three-dimensional memory includes a gate stack structure including a core area and a step area which are disposed in juxtaposition and in direct contact in a first direction; a dummy separation structure penetrating through the step area in the first direction; and a gate separation structure penetrating through the core area in the first direction, the gate separation structure having a first end in contact with the dummy separation structure in the first direction, the dummy separation structure having a second end in contact with the gate separation structure in the first direction, and the first end being located within the second end.

First claim

What is claimed is:

1. A three-dimensional memory, comprising:
a gate stack structure comprising a core area and a step area which are disposed in juxtaposition and in direct contact in a first direction;
a dummy separation structure penetrating through the step area in the first direction; and
a gate separation structure penetrating through the core area in the first direction, the gate separation structure having a first end in contact with the dummy separation structure in the first direction, the dummy separation structure having a second end in contact with the gate separation structure in the first direction, and the first end being located within the second end.

2. The three-dimensional memory of claim 1 , wherein the second end comprises two holding sub-parts, the first end is located between the two holding sub-parts in a second direction perpendicular to the first direction and is in direct contact with the two holding sub-parts.

3. The three-dimensional memory of claim 2 , wherein widths of the holding sub-parts in the second direction perpendicular to the first direction gradually increase from the step area towards the core area in the first direction.

4. The three-dimensional memory of claim 2 , wherein the second end further comprises a connection sub-part which is connected with the two holding sub-parts.

5. The three-dimensional memory of claim 4 , wherein the connection sub-part is in direct contact with the first end.

6. The three-dimensional memory of claim 1 , wherein the dummy separation structure further comprises a second extending part which is disposed in juxtaposition to and in direct contact with the second end.

7. The three-dimensional memory of claim 6 , wherein the second extending part extends in the first direction.

8. The three-dimensional memory of claim 6 , wherein a width of the second end in a second direction perpendicular to the first direction is greater than a width of the second extending part in the second direction.

9. The three-dimensional memory of claim 8 , wherein the width of the second end in the second direction gradually increases from the step area towards the core area in the first direction.

10. The three-dimensional memory of claim 8 , wherein the width of the second end in the second direction first gradually increases and then gradually decreases from the step area towards the core area in the first direction.

11. The three-dimensional memory of claim 1 , wherein a material of the dummy separation structure is an insulation material.

12. The three-dimensional memory of claim 1 , wherein the gate separation structure further comprises a first extending part which is disposed in juxtaposition to and in direct contact with the first end, and the first end is surrounded by the first extending part and the second end together on the circumference.

13. The three-dimensional memory of claim 12 , wherein the first extending part extends in the first direction.

14. The three-dimensional memory of claim 12 , wherein a width of at least part of the first end in a second direction perpendicular to the first direction is greater than a width of the first extending part in the second direction.

15. The three-dimensional memory of claim 14 , wherein a width of the first end in the second direction gradually increases from the core area towards the step area in the first direction.

16. The three-dimensional memory of claim 14 , wherein a width of the first end in the second direction first gradually increases and then gradually decreases from the core area towards the step area in the first direction.

17. The three-dimensional memory of claim 1 , wherein the first end extends into the step area in the first direction.

18. The three-dimensional memory of claim 1 , wherein a maximum width of the first end in a second direction perpendicular to the first direction is not greater than a minimum width of the second end in the second direction.

19. The three-dimensional memory of claim 1 , wherein the gate separation structure comprises a conductive structure and an electric insulation layer located between the conductive structure and the gate stack structure in the second direction perpendicular to the first direction.

20. The three-dimensional memory of claim 1 , wherein the second end comprises two holding sub-parts, the first end is located between the two holding sub-parts in the second direction perpendicular to the first direction and is in direct contact with the two holding sub-parts, the three-dimensional memory further comprises:
a plurality of channel structures located in the core area, the plurality of channel structures penetrating through the core area in a third direction intersected with the first direction and the second direction; and
a plurality of dummy channel structures located in the step area, the plurality of dummy channel structures penetrating through the step area in the third direction.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xu Zongke
• Yuan Bin
• Zhang Qiangwei
• Xu Bo

Classifications

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title