Storage device and operating method thereof

Patent metadata

Field	Value
Publication number	US-9728265-B2
Application number	US-201615055906-A
Country	US
Kind code	B2
Filing date	Feb 29, 2016
Priority date	Sep 17, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

There are provided a storage device and an operating method thereof. A storage device includes a string including a plurality of memory cells, peripheral circuits for, in a read operation of a selected memory cell, applying a read voltage to a selected word line electrically coupled to the selected memory cell, and selectively applying a first pass voltage and a second pass voltage higher than the first pass voltage to unselected word lines electrically coupled to the other unselected memory cells according to a position of the selected word line, and a controller for controlling the peripheral circuits.

First claim

What is claimed is:

1. A storage device comprising:
a string configured to include a first memory cell group and a second memory cell group, wherein the first memory cell group is adjacent to a drain select transistor, and the second memory cell group is adjacent to a source select transistor;
peripheral circuits configured to, in a read operation of a selected memory cell included in the first or the second memory cell group, apply a read voltage to a selected word line electrically coupled to the selected memory cell, and selectively apply a first pass voltage and a second pass voltage higher than the first pass voltage to unselected word lines electrically coupled to unselected memory cells,
wherein the first pass voltage is applied to all the unselected word lines when the selected memory cell is included in the second memory cell group, and applied to unselected word lines electrically coupled to the first memory cell group when the selected memory cell is included in the first memory cell group, and the second pass voltage is applied to unselected word lines electrically coupled to the second memory cell group when the selected memory cell is included in the first memory cell group; and
a controller configured to control the peripheral circuits.

2. The storage device of claim 1 , wherein the peripheral circuits include:
a voltage generation circuit configured to generate the read voltage, the first pass voltage, or the second pass voltage in response to an operation signal;
a row decoder configured to transmit a voltage generated by the voltage generation circuit to the selected word line and the unselected word lines in response to a row address;
a column decoder configured to transmit/receive data through a bit line electrically coupled to the string in response to a column address; and
an input/output circuit configured to receive a command from an outside source or device to transmit the received command to the controller or transmit/receive data to/from the outside source or device.

3. The storage device of claim 1 , wherein the string is formed into a two-dimensional structure in which the memory cells are horizontally arranged on a substrate, a three-dimensional structure in which the memory cells are vertically stacked in an I shape on the substrate, or a three-dimensional structure in which the memory cells are vertically stacked in a U shape on the substrate.

4. The storage device of claim 3 , wherein, when the string is formed into the two-dimensional structure or formed in the I shape, the controller controls the peripheral circuits to:
apply the read voltage to the selected word line;
apply the second pass voltage to the unselected word lines electrically coupled to the second memory cell group; and
apply the first pass voltage to all the unselected word lines or the unselected word lines electrically coupled to the first memory cell group.

5. The storage device of claim 3 , wherein, when the string is formed into the two-dimensional structure or formed in the I shape or U shape, the controller controls the peripheral circuits to:
divide the string into the first and second memory cell groups according to a resistance of the string, wherein the first memory cell group corresponds to a low resistance area and the second memory cell group corresponds to a high resistance area;
apply the read voltage to the selected word line;
if the selected word line is included in the second memory cell group, apply the first pass voltage to all the unselected word lines; and
if the selected word line is included in the first memory cells group, apply the second pass voltage to the unselected word lines included in the second memory cell group, and apply the first pass voltage to the unselected word lines included in the first memory cell group.

6. A storage device comprising:
a first memory cell group and a second memory cell group which are electrically coupled between a drain select transistor and a source select transistor;
peripheral circuits configured to perform a read operation of a selected memory cell included in the first or second memory cell group; and
a controller configured to control the peripheral circuits to, in the read operation, apply a first pass voltage, a second pass voltage, or the first and second pass voltages to unselected word lines electrically coupled to unselected memory cells according to a memory cell group between the first and second memory cell groups including the selected memory cell,
wherein the first pass voltage is applied to all the unselected word lines when the selected memory cell is included in the second memory cell group, and applied to unselected word lines electrically coupled to the first memory cell group when the selected memory cell is included in the first memory cell group, and the second pass voltage is applied to the unselected word lines when the selected memory cell is included in the first memory cell group.

7. The storage device of claim 6 , wherein the controller groups, as the first memory cell group, the memory cells adjacent to the drain select transistor among the memory cells, and groups, as the second memory cell group, the other memory cells adjacent to the source select transistor, and
wherein the controller controls the peripheral circuits to adjust a voltage applied to the unselected word lines according to a group including the selected memory cell among the first and second memory cell groups.

8. The storage device of claim 7 , wherein, if the selected memory cell is included in the first memory cell group, the controller controls the peripheral circuits to apply the first pass voltage to the unselected word lines electrically coupled to the first memory cell group, and apply the second pass voltage to the unselected word lines electrically coupled to the second memory cell group.

9. The storage device of claim 7 , wherein, if the selected memory cell is included in the second memory cell group, the controller controls the peripheral circuits to apply the first pass voltage to the all unselected word lines.

10. A method of operating a storage device, the method comprising:
grouping memory cells adjacent to a drain area of a string including a selected memory cell as a first memory cell group;
grouping the other memory cells adjacent to a source area of the string as a second memory cell group;
reading the selected memory cell; and
adjusting a pass voltage applied to unselected word lines electrically coupled to unselected memory cells according to a memory cell group between the first and second memory cell groups including the selected memory cell,
wherein, the first pass voltage is applied to all the unselected word lines when the selected memory cell is included in the second memory cell group, and applied to unselected word lines electrically coupled to the first memory cell group when the selected memory cell is included in the first memory cell group, and the second pass voltage is applied to unselected word lines electrically coupled to the second memory cell group when the selected memory cell is included in the first memory cell group.

Assignees

• Sk Hynix Inc

Inventors

• Lee Yeonghun

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title