Memory systems and methods for improved power management

Patent metadata

Field	Value
Publication number	US-12300307-B2
Application number	US-202318203591-A
Country	US
Kind code	B2
Filing date	May 30, 2023
Priority date	Nov 20, 2014
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

First claim

What is claimed is:

1. A command-buffer component comprising:
a controller interface to receive a controller command and a controller clock-enable signal;
a decoder to decode the controller command to a first number of memory-device clock-enable signals; and
memory interfaces to connect the command-buffer component to a second number of memory devices and convey the first number of memory-device clock-enable signals to respective ones of the second number of memory devices.

2. The command-buffer component of claim 1 , wherein the first number is less than the second number.

3. The command-buffer component of claim 2 , further comprising a register to store a value indicative of the first number.

4. The command-buffer component of claim 2 , the decoder to decode chip-select signals from the controller command, the chip-select signals to identify a subset of the memory devices, and direct the first number of clock-enable signals to the subset of the memory devices responsive to the decoded chip-select signals.

5. The command-buffer component of claim 1 , further comprising buffer-command ports to connect to data buffers that communicate data to and from the memory devices.

6. The command-buffer component of claim 5 , the buffer-command ports to selectively issue data-buffer-enable signals to subsets of the data buffers.

7. The command-buffer component of claim 6 , the buffer-command ports to selectively issue the data-buffer-enable signals responsive to the controller clock-enable signal.

8. The command-buffer component of claim 1 , the command-buffer component to awaken responsive to the controller clock-enable signal.

9. The command-buffer component of claim 1 , wherein the controller command includes address bits.

10. The command-buffer component of claim 9 , wherein the controller command includes an activate bit.

11. The command-buffer component of claim 1 , the decoder to receive the controller command at a first rate and retime the command to a slower second rate.

12. A method for selectively changing power states for a command-buffer component and subsets of a first number of memory devices connected to the command-buffer component, the method comprising:
receiving, at the command-buffer component, a controller clock-enable signal;
awakening the command-buffer component from a low-power state responsive to the controller clock-enable signal;
receiving, at the awakened command-buffer component, a power command with encoded chip-select signals;
decoding the encoded chip-select signals to a second number of memory-device clock-enable signals, the second number less than the first number; and
issuing the memory-device clock-enable signals to the second number of the memory devices to enable the second number of the memory devices.

13. The method of claim 12 , further comprising:
receiving, at the awakened command-buffer component, an activate command; and
forwarding the activate command to the first number of memory devices.

14. The method of claim 13 , further comprising:
receiving, at the awakened command-buffer component, a read command;
asserting chip-select signals, responsive to the read command, selecting a third number of the memory devices greater than the second number of the memory devices; and
issuing second memory-device clock-enable signals to the third number of the memory devices to enable the third number of the memory devices.

15. The method of claim 12 , wherein the memory devices communicate data via data-buffer components, the method further comprising sending a buffer clock-enable signal to the data-buffer components responsive to the controller clock-enable signal.

16. The method of claim 12 , further comprising reading a value from a configuration register, the value indicating the second number.

17. A command-buffer component comprising:
a controller interface to receive a controller command and a controller clock-enable signal;
means for decoding the controller command to a first number of memory-device clock-enable signals; and
memory interfaces to connect the command-buffer component to a second number of memory devices and convey the first number of memory-device clock-enable signals to respective ones of the second number of memory devices.

18. The command-buffer component of claim 17 , wherein the first number is less than the second number.

19. The command-buffer component of claim 18 , further comprising a register to store a value indicative of the first number.

20. The command-buffer component of claim 18 , the means for decoding to decode chip-select signals from the controller command, the chip-select signals identifying a subset of the memory devices, and directing the first number of clock-enable signals to the subset of the memory devices responsive to the decoded chip-select signals.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Harris James E

Classifications

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title