High density shield gate transistor structure and method of making

Patent metadata

Field	Value
Publication number	US-12295166-B2
Application number	US-202217581796-A
Country	US
Kind code	B2
Filing date	Jan 21, 2022
Priority date	Jan 21, 2022
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

A device and a method of making the device comprising, a semiconductor substrate layer and an epitaxial layer formed on the semiconductor substrate. One or more trenches are formed in the epitaxial layer, each trench having a pair of opposing sidewalls, wherein a distance between the opposing sidewalls is greater near a bottom of the trench than near a top of the trench, wherein the bottom of the trench is closer to the semiconductor substrate layer than the top.

First claim

What is claimed is:

1. A device comprising:
a semiconductor substrate layer;
an epitaxial layer on the semiconductor substrate;
one or more trenches in the epitaxial layer, each trench having a pair of opposing sidewalls, wherein a distance between the opposing sidewalls is greater near a bottom of the trench than near a top of the trench, wherein the bottom of the trench is closer to the semiconductor substrate layer than the top of the trench;
a trench-insulating layer lining each of the one or more trenches in the epitaxial layer; and
a conductive material layer formed on the trench-insulating layer in each of the one or more trenches in the epitaxial layer wherein a distance between opposing sides of the conductive material is greater near the bottom of the one or more trenches than near a top of the one or more trenches.

2. The device of claim 1 wherein each trench of the one or more trenches includes a bottom that is concave.

3. The device of claim 1 wherein the pair of opposing sidewalls include an inverse taper region wherein the distance between the opposing sidewalls increases with depth from the top into the epitaxial layer.

4. The device of claim 1 wherein the conductive material layer includes a gate electrode that is conductively coupled to a gate contact.

5. A device comprising:
a semiconductor substrate layer;
an epitaxial layer on the semiconductor substrate;
one or more trenches in the epitaxial layer, each trench having a pair of opposing sidewalls, wherein a distance between the opposing sidewalls is greater near a bottom of the trench than near a top of the trench, wherein the bottom of the trench is closer to the semiconductor substrate layer than the top of the trench;
a trench-insulating layer lining each of the one or more trenches in the epitaxial layer; and
a conductive material layer formed on the trench-insulating layer in each of the one or more trenches in the epitaxial layer wherein the conductive material layer formed on the trench-insulating layer includes a shield electrode formed near the bottom of the one or more trenches, the device further comprising gate insulating layer on top of the shield electrode and a gate electrode on top of the gate insulating layer, wherein the gate insulating layer is comprised of an insulating material and the gate electrode is made of a conductive material.

6. The device of claim 5 wherein a width of the gate electrode is less than a width of the shield electrode.

7. The device of claim 6 wherein the width of the gate electrode is a distance between opposing sides of the gate electrode and the width of the shield electrode is a distance between opposing sides of the shield electrode, wherein each of the opposing side walls of the gate electrode has a corresponding side wall of the shield electrode on the same side of the one or more trenches.

8. The device of claim 5 wherein a width of the gate electrode is equal to a width of the shield electrode.

9. The device of claim 1 wherein the one or more trenches includes two or more trenches wherein the pitch between trenches is 0.8 microns or less.

Assignees

• Alpha & Omega Semiconductor Int Lp

Inventors

• Bobde Madhur
• Lui Sik
• Zhang Lei
• Wang Xiaobin

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title