Formation of gate stacks comprising a threshold voltage tuning layer

Patent metadata

Field	Value
Publication number	US-12295163-B2
Application number	US-202217660389-A
Country	US
Kind code	B2
Filing date	Apr 22, 2022
Priority date	Dec 16, 2021
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

Threshold voltage (Vt) tuning layers may be sensitive to etching by reactants used to deposit overlying gate material, such as metal nitride. Methods for depositing Vt tuning layers are provided. In some embodiments Vt tuning layers may comprise a Vt tuning material in a neutral matrix. In some embodiments, processes for reducing or eliminating the etching of Vt tuning layers by halide reactants are described. In some embodiments a Vt tuning layer, such as a metal oxide layer, is treated by a nitridation process following deposition and prior to subsequent deposition of a metal nitride capping layer. In some embodiments an etch-protective layer, such as a NbO layer, is deposited over a Vt tuning layer prior to deposition of an overlying metal nitride layer.

First claim

What is claimed is:

1. A process for forming a gate stack comprising a threshold voltage (Vt) tuning metal oxide layer on a substrate in a reaction chamber comprising:
providing a substrate comprising a layer of high-k material in the reaction chamber;
depositing a Vt tuning metal oxide layer over the layer of high-k material;
depositing an etch-protective metal oxide layer comprising NbO over the Vt tuning metal oxide layer; and
depositing a metal nitride layer on the etch-protective metal oxide layer by a vapor deposition process using a vapor phase metal halide reactant.

2. The process of claim 1 , wherein the Vt tuning metal oxide layer comprises La y O x , Ga y O x , Al y O x , Nb y O x , V y O x , Mo y O x , Zn y O x , In y O x , or W y O x , wherein y is between 1 and 5 and x is between 1 and 10.

3. The process of claim 1 , wherein the metal nitride layer comprises TIN, AlN, MON, or TiAlN.

4. The process of claim 1 , wherein the metal nitride layer is deposited by a Chemical Vapor Deposition process or an Atomic Layer Deposition process.

5. The process of claim 1 , wherein the Vt tuning metal oxide layer comprises GaO or LaO, the metal nitride layer comprises TiN and the vapor phase metal halide reactant comprises TiCl 4 .

6. A process for forming a gate stack comprising a threshold voltage (Vt) tuning material layer on a substrate in a reaction chamber comprising:
providing a substrate comprising a layer of high-k material in the reaction chamber;
depositing a Vt tuning layer comprising a Vt tuning material in a neutral matrix over the layer of high-k material; and
depositing a metal nitride layer over the Vt tuning layer,
wherein the Vt tuning material comprises Ga, La or Hf.

7. The process of claim 6 , wherein the Vt tuning material comprises La or Hf.

8. The process of claim 6 , wherein the Vt tuning material comprises Ga y O x , Ga y N, Ga y C x , Ga y (ON) x , or Ga y (CN) x , wherein y is between 1 and 5 and x is between 1 and 10.

9. A process for forming a gate stack comprising a threshold voltage (Vt) tuning material layer on a substrate in a reaction chamber comprising:
providing a substrate comprising a layer of high-k material in the reaction chamber;
depositing a Vt tuning layer comprising a Vt tuning material in a neutral matrix over the layer of high-k material; and
depositing a metal nitride layer over the Vt tuning layer,
wherein the neutral matrix comprises Nb, In, Zn or Al.

10. A process for forming a gate stack comprising a threshold voltage (Vt) tuning material layer on a substrate in a reaction chamber comprising:
providing a substrate comprising a layer of high-k material in the reaction chamber;
depositing a Vt tuning layer comprising a Vt tuning material in a neutral matrix over the layer of high-k material; and
depositing a metal nitride layer over the Vt tuning layer,
wherein the neutral matrix comprises Nb y O x , Nb y N x , Nb y C x , In y O x , In y N x , In y C x , Zn y O x , Zn y C x , Zn y N x , Al y O x , Al y C x , or Al y N x , wherein y is between 1 and 5 and x is between 1 and 10.

11. A process for forming a gate stack comprising a threshold voltage (Vt) tuning material layer on a substrate in a reaction chamber comprising:
providing a substrate comprising a layer of high-k material in the reaction chamber;
depositing a Vt tuning layer comprising a Vt tuning material in a neutral matrix over the layer of high-k material; and
depositing a metal nitride layer over the Vt tuning layer,
wherein depositing the Vt tuning layer comprises a vapor deposition process comprising contacting the substrate with a vapor phase neutral matrix precursor and subsequently contacting the substrate with a vapor phase Vt tuning material precursor.

12. The process of claim 11 , wherein the neutral matrix precursor comprises at least one of Nb, In, Zn, or Al.

13. The process of claim 11 , wherein the Vt tuning material precursor comprises at least one of La, Hf, or Ga.

14. The process of claim 11 , wherein the substrate is contacted with an oxygen-containing reactant comprising O 2 .

15. The process of claim 14 , wherein the Vt tuning material comprises GaO and the neutral matrix comprises NbO.

Assignees

• Asm Ip Holding Bv

Inventors

• Tang Fu
• Shero Eric James
• Zhao Gejian
• Liu Eric Jen Cheng

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01344

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/01 Primary

  Manufacture or treatment · CPC title

• H10D64/685 Primary

  being perpendicular to the channel plane · CPC title