Retention voltages for integrated circuits

Patent metadata

Field	Value
Publication number	US-9620200-B1
Application number	US-201615081869-A
Country	US
Kind code	B1
Filing date	Mar 26, 2016
Priority date	Mar 26, 2016
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.

First claim

What is claimed is:

1. An integrated circuit, comprising:
functional circuitry configured to store one or more data bits; and
retention mode circuitry coupled to the functional circuitry and configured to provide a plurality of retention voltages to the functional circuitry, wherein the retention mode circuitry comprises:
a first circuitry configured to provide a first retention voltage to the functional circuitry, wherein the first circuitry comprises:
a first diode device; and
a first transistor device, a second diode device, or combinations thereof; and

a second circuitry configured to provide a second retention voltage to the functional circuitry, wherein the second circuitry comprises a plurality of second transistor devices;

wherein the functional circuitry is configured to be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.

2. The integrated circuit of claim 1 , wherein:
the functional circuitry comprises a memory device, a retention latch, a retention flop, or combinations thereof; and
the functional circuitry in the data retention mode is configured to maintain the storage of the one or more data bits if at least a minimum voltage is provided to the functional circuitry, and wherein the first retention voltage and the second retention voltage are each greater than or equal to the minimum voltage.

3. The integrated circuit of claim 1 , wherein the functional circuitry is coupled between a positive voltage supply node and a reference voltage node, and wherein the retention mode circuitry is coupled between the reference voltage node and a negative voltage supply node.

4. The integrated circuit of claim 3 , further comprising reference voltage circuitry configured to produce a reference voltage at the reference voltage node, wherein the reference voltage circuitry comprises:
the retention mode circuitry; and
active mode circuitry configured to place the functional circuitry in an active mode when the active mode circuitry is enabled, wherein the functional circuitry in the active mode is configured to allow a read or write access to the functional circuitry.

5. The integrated circuit of claim 4 , wherein the first retention voltage provided to the functional circuitry is based on a first reference voltage produced by the first circuitry at the reference voltage node, and wherein the second retention voltage provided to the functional circuitry is based on a second reference voltage produced by the second circuitry at the reference voltage node.

6. The integrated circuit of claim 5 , wherein the first reference voltage is greater than the second reference voltage, and wherein the first retention voltage is less than the second retention voltage.

7. The integrated circuit of claim 1 , wherein the first retention voltage is less than the second retention voltage.

8. The integrated circuit of claim 1 , wherein the first circuitry is coupled to a first leg and the second circuitry is coupled to a second leg, and wherein one of the first leg or the second leg is enabled to hold the functional circuitry in the data retention mode.

9. The integrated circuit of claim 1 , wherein the first circuitry or the second circuitry is configured to be enabled dynamically in response to one or more environmental conditions.

10. The integrated circuit of claim 1 , wherein the first circuitry comprises the first diode device, the second diode device, and the first transistor device coupled in series, wherein the first diode device is an NMOS diode, the second diode device is an NMOS diode, and the first transistor device is a PMOS transistor.

11. The integrated circuit of claim 1 , wherein the first circuitry comprises the first diode device and the second diode device coupled in parallel, wherein the first diode device is a NMOS diode and the second diode device is a PMOS diode.

12. The integrated circuit of claim 1 , wherein the first circuitry comprises the first circuitry comprises the first diode device, the transistor device, and the second diode device coupled in series, and wherein a switch device is configured to bypass the second diode device, wherein the first diode device is a NMOS diode, the second diode device is a NMOS diode, the switch device is a NMOS transistor, and the first transistor device is a NMOS transistor having a gate configured to receive a controllable voltage.

13. The integrated circuit of claim 1 , wherein the plurality of second transistor devices comprises a plurality of n-type transistor devices coupled in series, and wherein no diode devices are included in the second circuitry.

14. An integrated circuit, comprising:
functional circuitry coupled between a positive voltage supply node and a reference voltage node and configured to store one or more data bits; and
reference voltage circuitry coupled between the reference voltage node and a negative voltage supply node and configured to provide one or more retention voltages to the functional circuitry, wherein the reference voltage circuitry comprises:
at least a first n-type transistor device having a gate configured to receive a first controllable voltage, and wherein the one or more retention voltages is based on varying the first controllable voltage;

wherein the functional circuitry is configured to be held in a data retention mode when the one or more retention voltages is provided to the functional circuitry.

15. The integrated circuit of claim 14 , wherein the one or more retention voltages provided to the functional circuitry is based on one or more reference voltages produced by the reference voltage circuitry at the reference voltage node, and wherein the one or more reference voltages is produced based on varying the first controllable voltage.

16. The integrated circuit of claim 14 , wherein the reference voltage circuitry comprises a current mirror circuit having a voltage-controlled current source, wherein the current mirror circuit includes the first n-type transistor device, and wherein the first controllable voltage received by the gate is varied based on the voltage-controlled current source.

17. The integrated circuit of claim 14 , wherein the first controllable voltage is varied based on a first voltage regulator coupled to the gate of the first n-type transistor device.

18. The integrated circuit of claim 17 , wherein the reference voltage circuitry comprises the first n-type transistor device coupled with a second n-type transistor device having a gate configured to receive a second controllable voltage, wherein the second controllable voltage is varied based on a second voltage regulator coupled to the gate of the second n-type transistor device, and wherein the one or more retention voltages is based on varying the first controllable voltage and varying the second controllable voltage.

19. An integrated circuit, comprising:
functional circuitry configured to store one or more data bits; and
retention mode circuitry coupled to the functional circuitry and configured to provide a plurality of retention voltages to the functional circuitry, wherein the retention mode circuitry comprises:
a first circuitry configured to provide a first retention voltage to the functional circuitry, wherein the first circuitry comprises a diode device; and
a second circuitry configured to provide a second retention voltage to the functional circuitry, wherein the second circuitry comprises a plurality of transistor devices;

wherein the functional circuitry is conf

Assignees

• Advanced Risc Mach Ltd

Inventors

• Mangal Sanjay
• Yeung Gus
• Kinkade Martin Jay
• Mathur Rahul
• Sandhu Bal S
• Lattimore George Mcneil

Classifications

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/412

  using field-effect transistors only · CPC title