High aspect ratio source or drain structures with abrupt dopant profile

Patent metadata

Field	Value
Publication number	US-12288808-B2
Application number	US-202318370586-A
Country	US
Kind code	B2
Filing date	Sep 20, 2023
Priority date	Sep 24, 2019
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin;
a gate stack over the fin;
a first epitaxial source or drain structure at a first end of the fin; and
a second epitaxial source or drain structure at a second end of the fin, the first and second epitaxial source or drain structures comprising silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic, wherein the first and second epitaxial source or drain structures have a depth of phosphorous substantially the same as a depth of arsenic.

2. The integrated circuit structure of claim 1 , wherein the depth of phosphorous is within approximately 1 nanometer of the depth of arsenic.

3. The integrated circuit structure of claim 1 , wherein the first and second source or drain structures have a resistivity of less than approximately 0.35 mOhm·cm.

4. The integrated circuit structure of claim 1 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

5. The integrated circuit structure of claim 1 , further comprising:
a first conductive contact on the first epitaxial source or drain structure; and
a second conductive contact on the second epitaxial source or drain structure.

6. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin;
forming a gate stack over the fin;
forming a first epitaxial source or drain structure at a first end of the fin; and
forming a second epitaxial source or drain structure at a second end of the fin, the first and second epitaxial source or drain structures comprising silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic, wherein the first and second epitaxial source or drain structures have a depth of phosphorous substantially the same as a depth of arsenic.

7. The method of claim 6 , wherein the depth of phosphorous is within approximately 1 nanometer of the depth of arsenic.

8. The method of claim 6 , wherein the first and second source or drain structures have a resistivity of less than approximately 0.35 mOhm·cm.

9. The method of claim 6 , further comprising:
forming first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

10. The method of claim 6 , further comprising:
forming a first conductive contact on the first epitaxial source or drain structure; and
forming a second conductive contact on the second epitaxial source or drain structure.

11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin;
a gate stack around the fin;
a first epitaxial source or drain structure at a first end of the fin; and

a second epitaxial source or drain structure at a second end of the fin, the first and second epitaxial source or drain structures comprising silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic, wherein the first and second epitaxial source or drain structures have a depth of phosphorous substantially the same as a depth of arsenic.

12. The computing device of claim 11 , further comprising:
a memory coupled to the board.

13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14. The computing device of claim 11 , further comprising:
a camera coupled to the board.

15. The computing device of claim 11 , further comprising:
a display coupled to the board.

16. The computing device of claim 11 , further comprising:
a battery coupled to the board.

17. The computing device of claim 11 , further comprising:
an antenna coupled to the board.

18. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

19. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

20. The computing device of claim 11 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

Assignees

• Intel Corp

Inventors

• Keech Ryan
• Murthy Anand S
• Minutillo Nicholas G
• Vishwanath Suresh
• Hasan Mohammad
• Guha Biswajeet
• Rafique Subrina

Classifications

• H10D62/834

  further characterised by the dopants · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title