Semiconductor package

Patent metadata

Field	Value
Publication number	US-12288743-B2
Application number	US-202217655573-A
Country	US
Kind code	B2
Filing date	Mar 21, 2022
Priority date	Jun 25, 2021
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

A semiconductor package includes a lower substrate that includes a lower wiring layer; a semiconductor chip disposed on the lower substrate, and an upper substrate disposed on the semiconductor chip. The upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface. The lower surface of the upper substrate includes a cavity region that overlaps the semiconductor chip in a first direction, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate. The cavity region and the plurality of channel regions are defined by the plurality of protruding structures.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a lower substrate that includes a lower wiring layer;
a semiconductor chip disposed on the lower substrate, wherein the semiconductor chip is electrically connected to the lower wiring layer;
an upper substrate disposed on the semiconductor chip, wherein the upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface;
a connection structure disposed between the lower substrate and the upper substrate, wherein the connection structure electrically connects the lower wiring layer and the upper wiring layer;
an encapsulant that fills a space between the lower substrate and the upper substrate, and seals at least a portion of each of the semiconductor chip and the connection structure; and
a connection bump disposed below the lower substrate, wherein the connection bump is electrically connected to the lower wiring layer,
wherein the lower surface of the upper substrate includes a cavity region that overlaps the semiconductor chip in a first direction that is perpendicular to the lower surface, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate,
wherein the cavity region and the plurality of channel regions are defined by the plurality of protruding structures.

2. The semiconductor package of claim 1 , wherein the cavity region is surrounded by the plurality of protruding structures,
wherein the plurality of channel regions extend between the plurality of protruding structures and are spaced apart from each other.

3. The semiconductor package of claim 1 , wherein the upper substrate further comprises a first solder resist layer that provides the lower surface, and a second solder resist layer disposed below the first solder resist layer and that provides the plurality of protruding structures.

4. The semiconductor package of claim 3 , wherein the upper substrate further comprises an insulating layer on which the upper wiring layer is disposed,
wherein the first and second solder resist layers are sequentially stacked below the insulating layer,
wherein the plurality of channel regions expose the first solder resist layer or the insulating layer in the first direction.

5. The semiconductor package of claim 1 , wherein the lower surface of the upper substrate has a first surface that corresponds to the cavity region and a second surface that corresponds to the plurality of channel regions,
wherein the first surface and the second surface are substantially coplanar.

6. The semiconductor package of claim 1 , wherein the lower surface of the upper substrate has a first surface that corresponds to the cavity region and a second surface that corresponds to the plurality of channel regions,
wherein the second surface is located higher than the first surface.

7. The semiconductor package of claim 1 , wherein at least a portion of the plurality of protruding structures include an opening that exposes at least a portion of the upper wiring layer,
wherein the connection structure is disposed below the exposed portion of the plurality of protruding structures, and is electrically connected to the upper wiring layer through the opening.

8. The semiconductor package of claim 7 , wherein the connection structure includes a contact portion that fills the opening, and a body portion that extends from the contact portion to an upper surface of the lower substrate,
wherein the body portion has a convex side surface that has a maximum width in a second direction that is perpendicular to the first direction that is greater than a maximum width of the contact portion.

9. The semiconductor package of claim 1 , wherein, in the first direction, a height from an upper surface of the upper substrate to the lower surface thereof is from about 0.075 mm to about 0.085 mm,
a height between the upper substrate and the lower substrate is from about 0.135 mm to about 0.165 mm,
a height from an upper surface of the lower substrate to a lower surface thereof is from about 0.085 mm to about 0.095 mm, and
a height of the connection bump is from about 0.125 mm to about 0.135 mm.

10. The semiconductor package of claim 9 , wherein, in the first direction, a height of the plurality of protruding structures is in a range of from about 0.01 mm to about 0.02 mm.

11. The semiconductor package of claim 1 , wherein the upper substrate further includes a plurality of patch structures that protrude from the lower surface, wherein the plurality of patch structures are located in the cavity region and overlap the semiconductor chip.

12. A semiconductor package, comprising:
a lower substrate that includes a lower wiring layer;
a semiconductor chip disposed on the lower substrate, wherein the semiconductor chip is electrically connected to the lower wiring layer;
an upper substrate disposed on the semiconductor chip, wherein the upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface; and
a connection structure disposed between the lower substrate and the upper substrate, wherein the connection structure electrically connects the lower wiring layer and the upper wiring layer,
wherein the lower surface of the upper substrate includes a cavity region surrounded by the plurality of protruding structures, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate and pass between the plurality of protruding structures.

13. The semiconductor package of claim 12 , wherein the plurality of channel regions include a plurality of first channel regions that extend from the cavity region toward the edge of the upper substrate.

14. The semiconductor package of claim 13 , wherein the plurality of first channel regions have a line width in a range of from about 2 μm to about 50 μm.

15. The semiconductor package of claim 13 , wherein the plurality of channel regions further include a plurality of second channel regions that intersect the plurality of first channel regions.

16. The semiconductor package of claim 12 , wherein the cavity region has a planar area that is greater than a planar area of the semiconductor chip,
wherein the semiconductor chip is located in the cavity region.

17. A semiconductor package, comprising:
a lower substrate;
a semiconductor chip disposed on the lower substrate;
an upper substrate disposed on the semiconductor chip, wherein the upper substrate includes a lower surface that faces the semiconductor chip, and a plurality of protruding structures disposed below the lower surface, wherein the plurality of protruding structures do not overlap the semiconductor chip in a first direction that is perpendicular to the lower surface; and
a connection structure disposed below the plurality of protruding structures, wherein the connection structure extends in the first direction and electrically connects the upper substrate and the lower substrate,
wherein the lower surface of the upper substrate includes a cavity region that is surrounded by the plurality of protruding structures, and a plurality of first channel regions that extend from the cavity region toward an edge of the upper substrate and that pass between the plurality of protruding structures.

18. The semiconductor package of claim 17 , wherein the lower surface of the upper substrate further includes a plurality of second channel

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Junwoo
• Kim Seunghwan
• Kim Jungjoo
• Lee Yongkwan
• Jang Dongju

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W90/401 Primary

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title