Programmable interposer using RRAM platform

Patent metadata

Field	Value
Publication number	US-12284924-B2
Application number	US-202217697974-A
Country	US
Kind code	B2
Filing date	Mar 18, 2022
Priority date	Mar 18, 2022
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

According to various embodiments, there may be provided an interposer. The interposer including: a substrate; a dielectric layer disposed on the substrate; a via disposed entirely within the dielectric layer; a resistive film layer disposed to line the via; a metal interconnect disposed in the resistive layer lined via; and a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.

First claim

The invention claimed is:

1. An interposer comprising:
a substrate;
a dielectric layer disposed on the substrate;
a via disposed entirely within the dielectric layer;
a resistive film layer disposed to line the via;
a metal interconnect disposed in the resistive layer lined via; and
a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.

2. The interposer of claim 1 ,
wherein the via includes a first end and a second end opposite the first end and sides extending vertically from the first end to the second end,
wherein the resistive film layer lines the sides and the first end of the via, the resistive film layer including a first side portion, a second side portion, and a first end portion, the second side portion opposite the first side portion,
wherein the metal interconnect includes a first end and a second end opposite the first end, the first end of the metal interconnect facing the substrate is entirely surrounded by the resistive film layer and the second end of the metal interconnect is in direct contact with the dielectric layer, and
wherein the first metal line is directly connected to the metal interconnect, the second metal line is directly connected an outer surface of the resistive film layer at the first point, and the third metal line directly connected to the outer surface of the resistive film layer at the second point.

3. The interposer of claim 2 , wherein the second end of the metal interconnect extends above the resistive film layer.

4. The interposer of claim 2 , wherein the substrate comprises silicon.

5. The interposer of claim 2 , wherein the dielectric layer comprises silicon nitride and silicon dioxide with tetraethyl orthosilicate, silicon nitride, thermal oxide, or any low-K dielectric material.

6. The interposer of claim 2 , wherein the metal interconnect comprises copper, platinum, ruthenium, or tantalum nitride.

7. The interposer of claim 2 , wherein the via is cylindrically shaped and has a diameter of 50 nm to 200 nm.

8. The interposer of claim 2 , wherein the resistive film layer comprises hafnium oxide, tantalum oxide, or titanium oxide.

9. The interposer of claim 2 , wherein the resistive film layer is a continuous layer.

10. The interposer of claim 2 , wherein the first point is opposite the second point.

11. The interposer of claim 2 , wherein the first metal line is configured to be electrically connected to a control device.

12. The interposer of claim 11 , wherein the second metal line is configured to be electrically connected to a second chip and the third metal line is configured to be electrically connected to a third chip.

13. The interposer of claim 12 , wherein the third metal line is configured to be electrically connected to a through silicon via.

14. The interposer of claim 11 , wherein the second metal line becomes electrically connected to the metal interconnect when a potential difference between the first metal line and the second metal line exceeds a threshold voltage difference and wherein the third metal line becomes electrically connected to the metal interconnect when a potential difference between the first metal line and the third metal line exceeds the threshold voltage difference.

15. The interposer of claim 11 , wherein the first metal line is configured to receive a variable voltage from the control device.

16. The interposer of claim 11 , wherein the control device is a controller chip or a PN junction device.

17. The interposer of claim 11 , wherein the first metal line is provided in a first metal layer and wherein the second metal line and the third metal line are provided in a second metal layer.

18. The interposer of claim 11 , wherein the plurality of metal lines includes a fourth metal line connected to the resistive film layer at a third point.

19. A method of forming an interposer, the method comprising:
forming a dielectric layer disposed on a substrate;
forming a via disposed entirely within the dielectric layer;
forming a resistive film layer disposed to line the via;
forming a metal interconnect disposed in the resistive layer lined via; and
forming a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.

20. The method of claim 19 ,
wherein the via includes a first end and a second end opposite the first end and sides extending vertically from the first end to the second end,
wherein the resistive film layer lines the sides and the first end of the via, the resistive film layer including a first side portion, a second side portion, and a first end portion, the second side portion opposite the first side portion,
wherein the metal interconnect includes a first end and a second end opposite the first end, the first end of the metal interconnect facing the substrate is entirely surrounded by the resistive film layer and the second end of the metal interconnect is in direct contact with the dielectric layer, and
wherein the first metal line is directly connected to the metal interconnect, the second metal line is directly connected an outer surface of the resistive film layer at the first point, and the third metal line directly connected to the outer surface of the resistive film layer at the second point.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Leong Lup San
• Tan Juan Boon
• Lin Benfu
• Jiang Yi

Classifications

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10N70/021

  Formation of switching materials, e.g. deposition of layers · CPC title

• H10B63/00

  Resistance change memory devices, e.g. resistive RAM [ReRAM] devices · CPC title

• H10N70/011

  Manufacture or treatment of multistable switching devices · CPC title