Gate driver and display device having the same

Patent metadata

Field	Value
Publication number	US-12283223-B2
Application number	US-202318125135-A
Country	US
Kind code	B2
Filing date	Mar 23, 2023
Priority date	Aug 16, 2022
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

Provided is a gate driver comprising an inverter inverting a start signal to generate an inverted start signal, a first driver including a first stage generating a bias gate signal to initialize a light emitting element of each of pixels in response to the inverted start signal, and a second driver including a second stage generating a write gate signal to apply data voltages to the pixels in response to the start signal. Accordingly, the gate driver may generate a plurality of gate signals using one start signal. In addition, since the gate driver generates a write gate signal and a bias gate signal using one start signal, a bias operation and a light emitting element initialization operation may be performed in a self-scan period without adding the start signal. Further, a size of the gate driver may be reduced, and accordingly, the gate driver may be efficiently disposed.

First claim

What is claimed is:

1. A gate driver of a display device comprising:
an inverter configured to invert a start signal to generate an inverted start signal;
a first driver including a first stage configured to generate a bias gate signal to initialize a light emitting element of each of pixels in the display device in response to the inverted start signal; and
a second driver including a second stage configured to generate a write gate signal to apply data voltages to the pixels in the display device in response to the start signal,
wherein the first driver further receives a first clock signal and a second clock signal whose phase is different than the first clock signal to generate the bias gate signal.

2. The gate driver of claim 1 , wherein the write gate signal has an activation period in a display scan period in which the data voltages are written to a storage capacitor of each of the pixels in the display device and in a self-scan period in which the data voltages are not written to the storage capacitor of each of the pixels in the display device.

3. The gate driver of claim 1 , wherein the bias gate signal has an activation period in a display scan period in which the data voltages are written to a storage capacitor of each of the pixels in the display device and in a self-scan period in which the data voltages are not written to the storage capacitor of each of the pixels in the display device.

4. The gate driver of claim 1 , wherein the inverter is configured to receive the first clock signal and the second clock signal to generate the inverted start signal.

5. The gate driver of claim 4 , wherein the second stage is configured to receive a third clock signal and a fourth clock signal to generate the write gate signal.

6. The gate driver of claim 1 , wherein each of the pixels in the display device includes:
a first pixel transistor including a control electrode connected to a first pixel node, a first electrode connected to a second pixel node, and a second electrode connected to a third pixel node;
a second pixel transistor including a control electrode configured to receive the write gate signal, a first electrode configured to receive the data voltages, and a second electrode connected to the second pixel node;
a third pixel transistor including a control electrode configured to receive a compensation gate signal, a first electrode connected to the third pixel node, and a second electrode connected to the first pixel node;
a fourth pixel transistor including a control electrode configured to receive an initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the first pixel node;
a fifth pixel transistor including a control electrode configured to receive an emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to the second pixel node;
a sixth pixel transistor including a control electrode configured to receive the emission signal, a first electrode connected to the third pixel node, and a second electrode connected to a fourth pixel node;
a seventh pixel transistor including a control electrode configured to receive the bias gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to the fourth pixel node;
a storage capacitor including a first electrode configured to receive the first power voltage and a second electrode connected to the first pixel node; and
the light emitting element including a first electrode connected to the fourth pixel node and a second electrode configured to receive a second power voltage.

7. The gate driver of claim 1 , wherein the first stage includes:
a 1-1th stage transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive a first input signal, and a second electrode connected to a 1-1th stage node;
a 1-2th stage transistor including a control electrode connected to a 1-2th stage node, a first electrode configured to receive a high voltage, and a second electrode connected to a 1-3th stage node;
a 1-3th stage transistor including a control electrode connected to a 1-4th stage node, a first electrode configured to receive the second clock signal, and a second electrode connected to the 1-3th stage node;
a 1-4th stage transistor including a control electrode connected to the 1-1th stage node, a first electrode configured to receive the first clock signal, and a second electrode connected to the 1-2th stage node;
a 1-5th stage transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive a low voltage, and a second electrode connected to the 1-2th stage node;
a 1-6th stage transistor including a control electrode configured to receive the second clock signal, a first electrode connected to a 1-5th stage node, and a second electrode connected to a 1-6th stage node;
a 1-7th stage transistor including a control electrode connected to a 1-7th stage node, a first electrode configured to receive the second clock signal, and a second electrode connected to the 1-5th stage node;
a 1-8th stage transistor including a control electrode connected to the 1-1th stage node, a first electrode configured to receive the high voltage, and a second electrode connected to the 1-6th stage node;
a 1-9th stage transistor including a control electrode connected to the 1-6th stage node, a first electrode configured to receive the high voltage, and a second electrode connected to an output terminal of the first stage;
a 1-10th stage transistor including a control electrode connected to the 1-4th stage node, a first electrode configured to receive the low voltage, and a second electrode connected to the output terminal of the first stage;
a 1-11th stage transistor including a control electrode configured to receive the low voltage, a first electrode connected to the 1-2th stage node, and a second electrode connected to the 1-7th stage node;
a 1-12th stage transistor including a control electrode configured to receive the low voltage, a first electrode connected to the 1-1th stage node, and a second electrode connected to the 1-4th stage node;
a 1-1th stage capacitor including a first electrode configured to receive the high voltage and a second electrode connected to the 1-6th stage node;
a 1-2th stage capacitor including a first electrode connected to the 1-7th stage node and a second electrode connected to the 1-5th stage node; and
a 1-3th stage capacitor including a first electrode connected to the 1-4th stage node and a second electrode connected to the 1-3th stage node.

8. The gate driver of claim 7 , wherein the first stage outputting a first bias gate signal in one frame is configured to receive the inverted start signal as the first input signal.

9. The gate driver of claim 1 , wherein the second stage includes:
a 2-1th stage transistor including a control electrode configured to receive a third clock signal, a first electrode configured to receive a second input signal, and a second electrode connected to a 2-1th stage node;
a 2-2th stage transistor including a control electrode connected to a 2-2th stage node, a first electrode configured to receive a high voltage, and a second electrode connected to a first electrode of a 2-3th stage transistor;
the 2-3th stage transistor including a control electrode configured to receive a fourth clock signal, the first electrode connected to the second electrode of the 2-2th stage transistor, and a second electrode connected to the 2-1th stage node;
a 2-4th stage transistor including a control electrode connected to th

Assignees

• Samsung Display Co Ltd

Inventors

• Son Sungmin
• Song Jae-Jin
• Eom Kimyeong
• Lee Jungwoo

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title