Inverter, AMOLED compensation circuit and display panel

Patent metadata

Field	Value
Publication number	US-9311849-B2
Application number	US-201314062726-A
Country	US
Kind code	B2
Filing date	Oct 24, 2013
Priority date	Nov 21, 2012
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

An inverter is disclosed. The disclosed inverter includes first, second, third, and fourth transistors, where each of the first, second, third, and fourth transistors is a P-type thin film transistor. The inverter also includes a first capacitor. The inverter allows for wide voltage output swing performance and low power consumption.

First claim

What is claimed is:

1. An inverter, comprising:
a first, second, third, and fourth transistors, wherein each of the first, second, third, and fourth transistors is a P-type thin film transistor; and
a first capacitor,
wherein a gate of the first transistor is connected with a gate of the third transistor, and the gate of the first transistor and the gate of the third transistor are connected to an input terminal of a first signal,
wherein a source of the first transistor is connected with a source of the third transistor, and the source of the first transistor and the source of the third transistor are connected to an input terminal of a second signal,
wherein a drain of the first transistor is connected with a gate of the fourth transistor and a source of the second transistor at a first node,
wherein a gate of the second transistor is connected with an input terminal of a second clock signal, a drain of the second transistor is connected with a drain of the fourth transistor, and the drain of the second transistor and the drain of the fourth transistor are connected to an input terminal of a third signal,
wherein a drain of the third transistor is connected with a source of the fourth transistor, and the drain of the third transistor and the source of the fourth transistor are connected to a signal output terminal of the inverter,
wherein the first capacitor has one terminal connected with the first node and has another terminal connected with an input terminal of a first clock signal, and
wherein a high voltage signal is input to the input terminal of the second signal, and a low voltage signal is input to the input terminal of the third signal.

2. The inverter according to claim 1 , further comprising a second capacitor, of which one terminal is connected with the source of the third transistor and another terminal is connected with the drain of the third transistor.

3. A compensation circuit of an active matrix organic light-emitting diode display panel, the circuit comprising:
an inverter, comprising:
a first, second, third, and fourth transistors, wherein each of the first, second, third, and fourth transistors is a P-type thin film transistor; and
a first capacitor,
wherein a gate of the first transistor is connected with a gate of the third transistor, and the gate of the first transistor and the gate of the third transistor are connected to an input terminal of a first signal,
wherein a source of the first transistor is connected with a source of the third transistor, and the source of the first transistor and the source of the third transistor are connected to an input terminal of a second signal,
wherein a drain of the first transistor is connected with a gate of the fourth transistor and a source of the second transistor at a first node,
wherein a gate of the second transistor is connected with an input terminal of a second clock signal, a drain of the second transistor is connected with a drain of the fourth transistor, and the drain of the second transistor and the drain of the fourth transistor are connected to an input terminal of a third signal,
wherein a drain of the third transistor is connected with a source of the fourth transistor, and the drain of the third transistor and the source of the fourth transistor are connected to a signal output terminal of the inverter,
wherein the first capacitor has one terminal connected with the first node and has another terminal connected with an input terminal of a first clock signal, and
wherein a high voltage signal is input to the input terminal of the second signal, and a low voltage signal is input to the input terminal of the third signal.

4. The compensation circuit according to claim 3 , wherein the inverter further comprises a second capacitor, of which one terminal is connected with the source of the third transistor and another terminal is connected with the drain of the third transistor.

5. A display panel, comprising a compensation circuit for an active matrix organic light-emitting diodes display panel, wherein the compensation circuit comprises an inverter, the inverter comprising:
a first, second, third, and fourth transistors, wherein each of the first, second, third, and fourth transistors is a P-type thin film transistor; and
a first capacitor,
wherein a gate of the first transistor is connected with a gate of the third transistor, and the gate of the first transistor and the gate of the third transistor are connected to an input terminal of a first signal,
wherein a source of the first transistor is connected with a source of the third transistor, and the source of the first transistor and the source of the third transistor are connected to an input terminal of a second signal,
wherein a drain of the first transistor is connected with a gate of the fourth transistor and a source of the second transistor at a first node,
wherein a gate of the second transistor is connected with an input terminal of a second clock signal, a drain of the second transistor is connected with a drain of the fourth transistor, and the drain of the second transistor and the drain of the fourth transistor are connected to an input terminal of a third signal,
wherein a drain of the third transistor is connected with a source of the fourth transistor, and the drain of the third transistor and the source of the fourth transistor are connected to a signal output terminal of the inverter, wherein the first capacitor has one terminal connected with the first node and has another terminal connected with an input terminal of a first clock signal, and
wherein a high voltage signal is input to the input terminal of the second signal, and a low voltage signal is input to the input terminal of the third signal.

6. The display panel according to claim 5 , wherein the inverter further comprises a second capacitor, of which one terminal is connected with the source of the third transistor and another terminal is connected with the drain of the third transistor.

Assignees

• Shanghai Tianma Micro Elect Co

Inventors

• Qian Dong

Classifications

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H03K19/0027

  in field effect transistor circuits · CPC title

• G09G3/3225 Primary

  using an active matrix · CPC title