Lifetime indicator system

Patent metadata

Field	Value
Publication number	US-12282059-B2
Application number	US-202418666452-A
Country	US
Kind code	B2
Filing date	May 16, 2024
Priority date	Apr 19, 2016
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

First claim

What is claimed is:

1. A lifetime indicator system, comprising:
a plurality of different monitor devices configured to monitor different types of wear-out stresses in parallel, wherein one of the monitor devices is a first wear-out monitor device configured to record a wear-out stress without being powered;
a plurality of analog to digital converters (ADCs) electrically connected to respective ones of the monitor devices for receiving monitoring signals therefrom and configured to generate an output;
a memory device having stored therein a predetermined alert limit for each of the different types of wear-out stresses; and
a microprocessor connected to the ADCs and the memory device, the microprocessor configured to receive the output from each of the ADCs and to determine whether the predetermined alert limit has been reached for one or more of the different types of wear-out stresses based on the output.

2. The lifetime indicator system of claim 1 , wherein the lifetime indicator system is in sufficiently close proximity to a core circuit such that the monitor devices and the core circuit are simultaneously subjected to substantially the same wear-out stresses.

3. The lifetime indicator system of claim 2 , wherein the core circuit comprises an integrated circuit device integrated on a common substrate with the monitor devices.

4. The lifetime indicator system of claim 2 , wherein the core circuit comprises a transistor device, and the wear-out stresses comprise two or more of a voltage stress, a current stress, a temperature stress, a mechanical stress, a humidity stress and an electromagnetic stress that cause degradation of performance of the transistor device.

5. The lifetime indicator system of claim 1 , wherein the first wear-out monitor device comprises an atomic diffusion-based monitor device configured to generate a monitoring signal resulting from atomic diffusion caused by a temperature stress.

6. The lifetime indicator system of claim 1 , wherein the microprocessor is configured to employ artificial intelligence to determine whether the predetermined alert limit has been reached for one or more of the different types of wear-out stresses.

7. The lifetime indicator system of claim 1 , further comprising an energy harvesting device for at least partly powering the lifetime indicator system.

8. The lifetime indicator system of claim 1 , wherein the microprocessor is configured to transmit an alert upon determining that the predetermined alert limit has been reached for one or more of the different types of wear-out stresses.

9. The lifetime indicator system of claim 8 , wherein the transmitted alert is encrypted.

10. A lifetime indicator system, comprising:
a plurality of different monitor devices integrated and configured to monitor different types of wear-out stresses in parallel, wherein one of the monitor devices is a cumulative wear-out monitor device configured to record a cumulative effect of a wear-out stress;
a plurality of analog to digital converters (ADCs) electrically connected to respective ones of the monitor devices for receiving monitoring signals therefrom and configured to generate an output;
a memory device having stored therein a mission profile comprising a reference cumulative profile for each of the different types of the wear-out stresses; and
a microprocessor connected to the ADCs and the memory device, the microprocessor configured to receive the output from each of the ADCs, and to compare the output to the reference cumulative profiles to determine whether an alert limit has been reached for one or more of the wear-out stresses.

11. The lifetime indicator system of claim 10 , wherein the lifetime indictor system is in sufficiently close proximity to a core circuit such that the monitor devices and the core circuit are simultaneously subjected to substantially the same wear-out stresses.

12. The lifetime indicator system of claim 11 , wherein the wear-out stresses comprise two or more of a voltage stress, a current stress, a temperature stress, a mechanical stress, a humidity stress and an electromagnetic stress that cause degradation of performance of the core circuit.

13. The lifetime indicator system of claim 10 , wherein the cumulative wear-out monitor device is configured to record the cumulative effect of the wear-out stress without being powered.

14. The lifetime indicator system of claim 10 , wherein the cumulative wear-out monitor device comprises an atomic diffusion-based monitor device comprising:
a reservoir containing the diffusant; and
a diffusion region in communication with the reservoir such that the wear-out stress causes the charged diffusant to diffuse from the reservoir into the diffusion region.

15. The lifetime indicator system of claim 10 , wherein the microprocessor is configured to employ artificial intelligence to determine whether the alert limit has been reached for one or more of the wear-out stresses.

16. The lifetime indicator system of claim 10 where the monitor devices, the ADCs the microprocessor and the memory device are integrated in a common substrate.

17. A lifetime indicator system, comprising:
a plurality of different monitor devices configured to monitor different types of wear-out stresses in parallel;
a plurality of analog to digital converters (ADCs) electrically connected to respective ones of the monitor devices for receiving monitoring signals therefrom and configured to generate an output;
a memory device having stored therein a predetermined alert limit for each of the different types of wear-out stresses; and
a microprocessor connected to the ADCs and the memory device, the microprocessor configured to receive the output from each of the ADCs and to determine whether the predetermined alert limit has been reached for one or more of the different types of wear-out stresses based on the output,
wherein the microprocessor is configured to transmit an encrypted alert upon determining that the predetermined alert limit has been reached for one or more of the different types of wear-out stresses.

18. The lifetime indicator system of claim 17 , wherein one of the monitor devices is a cumulative wear-out monitor device configured to record a cumulative effect of a wear-out stress.

19. The lifetime indicator system of claim 18 , wherein the cumulative wear-out monitor device is further configured to record a wear-out stress without being powered.

20. The lifetime indicator system of claim 17 , wherein the lifetime indictor system is in sufficiently close proximity to a core circuit such that the monitor devices and the core circuit are simultaneously subjected to substantially the same wear-out stresses.

Assignees

• Analog Devices International Unlimited Co

Inventors

• Coyne Edward John
• O'Donnell Alan J
• Bradley Shaun
• Aherne David
• Boland David
• O'Dwyer Thomas G
• Heffernan Colm Patrick
• Manning Kevin B
• Forde Mark
• Clarke David J
• Looby Michael A

Classifications

• G01N27/041

  of a solid body · CPC title

• G01R31/2874

  related to temperature · CPC title

• G01R31/2879 Primary

  related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads · CPC title