Masked-vector-comparison instruction

Patent metadata

Field	Value
Publication number	US-12277420-B2
Application number	US-202118247595-A
Country	US
Kind code	B2
Filing date	Aug 17, 2021
Priority date	Oct 6, 2020
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

A masked-vector-comparison instruction specifies a source vector operand comprising a plurality of source data elements, a mask value, and a comparison target operand. In response to the masked-vector-comparison instruction, an instruction decoder 10 controls processing circuitry 16 to: for each active source data element of the source vector operand, determine whether the active source data element satisfies a comparison condition, based on a masked comparison between one or more compared bits of the active source data element and one or more compared bits of the comparison target operand, the mask value specifying a pattern of compared bits and non-compared bits within the comparison target operand and the active source data element; and generate a result value indicative of which of the source data elements of the source vector operand, if any, is an active source data element satisfying the comparison condition. This instruction is useful for variable length decoding operations.

First claim

The invention claimed is:

1. An apparatus comprising:
instruction decoder hardware configured to decode program instructions; and
processing circuitry configured to perform data processing in response to the program instructions decoded by the instruction decoder hardware; in which:
in response to decoding of a masked-vector-comparison instruction specifying a source vector operand comprising a plurality of source data elements, a mask value, and a comparison target operand, the instruction decoder hardware is configured to control the processing circuitry to:
for each active source data element of the source vector operand, determine whether the active source data element satisfies a comparison condition, based on a masked comparison between one or more compared bits of the active source data element and one or more compared bits of the comparison target operand, the mask value specifying a pattern of compared bits and non-compared bits within the comparison target operand and the active source data element, wherein for at least one encoding of the mask value, the mask value is configured to indicate that the pattern comprises, for a given active source data element, at least one compared bit and at least one non-compared bit; and
generate a result value indicative of which of the source data elements of the source vector operand, if any, is an active source data element satisfying the comparison condition.

2. The apparatus according to claim 1 , in which the instruction decoder hardware is configured to support the masked-vector-comparison instruction specifying an encoding of the mask value specifying different patterns of compared bits and non-compared bits for different source data elements of the source vector operand.

3. The apparatus according to claim 2 , in which the mask value comprises a mask vector operand comprising a plurality of mask data elements, each mask data element specifying a pattern of compared bits and non-compared bits for a corresponding source data element of the source vector operand.

4. The apparatus according to claim 2 , in which the mask value is specified within part of the source vector operand, and a predetermined subset of bits of a given source data element are non-compared bits specifying the pattern of compared bits and non-compared bits to be used for other bits of the given source data element.

5. The apparatus according to claim 1 , in which the mask value has an encoding which constrains the pattern of compared bits and non-compared bits to be the same for each active source data element.

6. The apparatus according to claim 1 , in which when at least one active source data element satisfies the comparison condition, the result value specifies a data value specified by an active source data element which satisfied the comparison condition.

7. The apparatus according to claim 6 , in which the data value specified by the result value comprises at least one non-compared bit of the active source data element which satisfied the comparison condition.

8. The apparatus according to claim 1 , in which when at least one active source data element satisfies the comparison condition, the result value specifies a value indicative of an element position of an active source data element within the source vector operand which satisfies the comparison condition.

9. The apparatus according to claim 1 , in which the result value is a result vector comprising a plurality of result data elements, and in response to the masked-vector-comparison instruction, the instruction decoder hardware is configured to control the processing circuitry to set each result data element of the result value corresponding to an active source data element of the source vector operand to a value depending on whether the corresponding active source data element satisfied the comparison condition.

10. The apparatus according to claim 9 , in which the processing circuitry is configured to cause a given result data element corresponding to an active source data element which does not satisfy the comparison condition to be set to one of:
a previous value of a portion of a destination vector register used to store the given result data element; and
a comparison fail indicating value indicating that the corresponding active source data element did not satisfy the comparison condition.

11. The apparatus according to claim 1 , in which the result value is a scalar value.

12. The apparatus according to claim 1 , in which the result value is a result vector comprising a plurality of result data elements, and in response to the masked-vector-comparison instruction, the instruction decoder hardware is configured to control the processing circuitry to set a selected result data element of the result value to a value indicative of which of the source data elements of the source vector operand, if any, is an active source data element satisfying the comparison condition.

13. The apparatus according to claim 12 , in which the masked-vector-comparison instruction specifies an element selection value indicating which result data element of the result vector is the selected result data element.

14. The apparatus according to claim 12 , in which the result vector is specified in a destination vector register, and in response to the masked-vector-comparison instruction, the instruction decoder hardware is configured to control the processing circuitry to cause one or more other result data elements other than the selected result data element to be set to a previous value of a portion of the destination vector register corresponding to the one or more other result data elements.

15. The apparatus according to claim 1 , in which when at least two active source data elements satisfy the comparison condition, the processing circuitry is configured to select a selected active source data element, from among the at least two active source data elements which satisfied the comparison condition, according to a predetermined order of preference, and to set the result value to a value indicative of the selected active source data element satisfying the comparison condition.

16. The apparatus according to claim 1 , in which when none of the active source data elements of the source vector operand satisfy the comparison condition, the processing circuitry is configured to cause the result value to be set to one of:
a previous value of a portion of a destination register used to store the result value; and
a comparison fail indicating value indicating that none of the active source data elements of the source vector operand satisfy the comparison condition.

17. The apparatus according to claim 1 , in which the result value comprises a predicate value comprising a plurality of predicate indications, each predicate indication indicative of whether a corresponding source data element of the source vector operand is an active source data element satisfying the comparison condition.

18. The apparatus according to claim 1 , in which the comparison target operand is the same for each active source data element.

19. A data processing method comprising:
decoding program instructions using an instruction decoder; and
in response to the program instructions decoded by the instruction decoder, performing data processing using processing circuitry; in which:
in response to decoding of a masked-vector-comparison instruction specifying a source vector operand comprising a plurality of source data elements, a mask value, and a comparison target operand, the processing circuitry is contr

Assignees

• Advanced Risc Mach Ltd

Inventors

• Eapen Jacob
• Boettcher Matthias Lothar
• VENU Balaji
• Botman François Christopher Jacques

Classifications

• G06F9/30038 Primary

  using a mask · CPC title

• G06F9/30018 Primary

  Bit or string instructions · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30021 Primary

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title