Packed data operation mask comparison processors, methods, systems, and instructions

Patent metadata

Field	Value
Publication number	US-2016154652-A1
Application number	US-201514966206-A
Country	US
Kind code	A1
Filing date	Dec 11, 2015
Priority date	Dec 29, 2011
Publication date	Jun 2, 2016
Grant date	—

Abstract

Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.

First claim

1 .- 20 . (canceled)

21 . An apparatus comprising:
a first packed data operation mask register to store a first packed data operation mask which is to have a first plurality of packed data operation mask bits; a second packed data operation mask register to store a second packed data operation mask which is to have a second plurality of packed data operation mask bits; a decode unit to decode a packed data operation mask comparison instruction, the packed data operation mask comparison instruction to indicate the first packed data operation mask register and to indicate the second packed data operation mask register, wherein each packed data operation mask bit of the first plurality is to correspond to a packed data operation mask bit of the second plurality in a corresponding position; and an execution unit coupled with the first and second packed data operation mask registers and coupled with the decode unit, the execution unit, in response to the packed data operation mask comparison instruction, to: modify a first flag to a first value if a result of a bitwise operation on each packed data operation mask bit of the first packed data operation mask and each corresponding packed data operation mask bit of the second packed data operation mask is zero, or otherwise modify the first flag to a second different value; and modify a second flag to one of the first and second values.

22 . The apparatus of claim 21 , wherein the first flag is a zero flag.

23 . The apparatus of claim 22 , wherein the first value is binary one and the second value is binary zero.

24 . The apparatus of claim 22 , wherein the second flag is a carry flag.

25 . The apparatus of claim 21 , wherein the first flag is a zero flag, wherein the second flag is a carry flag, and wherein the first value is binary one and the second value is binary zero.

26 . The apparatus of claim 21 , wherein the execution unit, in response to the instruction, is to modify the second flag to the first value if a comparison associated with the first and second packed data operation masks is met, or otherwise is to modify the second flag to the second value.

27 . The apparatus of claim 21 , wherein each of the first and second packed data operation masks is to have eight packed data operation mask bits.

28 . The apparatus of claim 21 , wherein each of the first and second packed data operation masks is to have sixteen packed data operation mask bits.

29 . The apparatus of claim 21 , wherein each of the first and second packed data operation masks is to have thirty two packed data operation mask bits.

30 . The apparatus of claim 21 , wherein each of the first and second packed data operation masks is to have sixty four packed data operation mask bits.

31 . The apparatus of claim 21 , wherein the first packed data operation mask register is to store the first packed data operation mask in only a portion of its bits.

32 . The apparatus of claim 31 , wherein the first packed data operation mask register comprises sixty-four bits, and wherein the first packed data operation mask is to have one of an eight, sixteen, and a thirty-two bit subset of the sixty-four bits.

33 . The apparatus of claim 21 , wherein the decode unit is also to decode a second instruction that is to indicate the first packed data operation mask register as a source for a packed data operation mask that is to be used to predicate a packed data operation.

34 . A method comprising:
receiving a packed data operation mask comparison instruction, the packed data operation mask comparison instruction indicating a first packed data operation mask that has a first plurality of packed data operation mask bits, indicating a second packed data operation mask that has a second plurality of packed data operation mask bits, wherein each packed data operation mask bit of the first plurality corresponds to a packed data operation mask bit of the second plurality in a corresponding position; and modifying a first flag to a first value if a result of a bitwise operation on each packed data operation mask bit of the first packed data operation mask and each corresponding packed data operation mask bit of the second packed data operation mask is zero, or otherwise modifying the first flag to a second different value; and modifying a second flag to one of the first and second values.

35 . The method of claim 34 , wherein modifying the first flag comprises modifying a zero flag.

36 . The method of claim 35 , wherein modifying the first flag comprises modifying the first flag to the first value of binary one or to the second value of binary zero.

37 . The method of claim 35 , wherein modifying the second flag comprises modifying a carry flag.

38 . The method of claim 34 , wherein modifying the second flag comprises modifying the second flag to the first value if a comparison associated with the first and second packed data operation masks is met, or otherwise modifying the second flag to the second value.

39 . The method of claim 34 , wherein the first packed data operation mask is stored in only a portion of all bits of the first packed data operation mask register.

40 . The method of claim 34 , further comprising receiving a masked packed data instruction indicating the first packed data operation mask as a predicate operand.

41 . An article of manufacture comprising:
a machine-readable storage medium, the machine-readable storage medium storing a packed data operation mask comparison instruction, the packed data operation mask comparison instruction to indicate a first packed data operation mask that is to have a first plurality of packed data operation mask bits and to indicate a second packed data operation mask that is to have a second plurality of packed data operation mask bits, wherein each packed data operation mask bit of the first plurality is to correspond to a packed data operation mask bit of the second plurality in a corresponding position, and the packed data operation mask comparison instruction if executed by a machine operable to cause the machine to perform operations comprising: modify a first architecturally-visible processor state element to a first value if a result of a bitwise operation on each packed data operation mask bit of the first packed data operation mask and each corresponding packed data operation mask bit of the second packed data operation mask is zero, or otherwise modify the first architecturally-visible processor state element to a second different value; and modify a second architecturally-visible processor state element to one of the first and second values.

42 . The article of manufacture of claim 41 , wherein the first architecturally-visible processor state element is a zero flag, and wherein the first value is binary one.

43 . The article of manufacture of claim 41 , wherein the instruction if executed by the machine is operative to cause the machine to modify the second architecturally-visible processor state element to the first value if a comparison associated with the first and second packed data operation masks is met, or otherwise modifying the second architecturally-visible processor state element to the second value.

Assignees

• Intel Corp

Inventors

• Toll Bret L
• Valentine Robert
• Corbal Jesus
• Ould-Ahmed-Vall Elmoustapha
• Charney Mark J

Classifications

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/30189 Primary

  according to execution mode, e.g. mode flag · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title