Testing bit values inside vector elements

Patent metadata

Field	Value
Publication number	US-2020225953-A1
Application number	US-201816629178-A
Country	US
Kind code	A1
Filing date	Jun 27, 2018
Priority date	Jul 10, 2017
Publication date	Jul 16, 2020
Grant date	—

Abstract

An apparatus and method of operating an apparatus are provided. The apparatus is responsive to a bit-testing instruction which specifies a source vector register and an index to perform a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits. The bit-testing procedure comprises, for each processed element of the plural elements, setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index. This bit-testing instruction thus enables increased performance of program code which is required to perform multiple bit tests and can be suitably formulated into a vectorised form.

First claim

1 . An apparatus comprising:
instruction decoding circuitry to decode instructions and generate control signals in dependence on the instructions; and data processing circuitry to perform data processing operations in response to the control signals generated by the instruction decoding circuitry, wherein the instruction decoding circuitry is responsive to a bit-testing instruction specifying a source vector register and an index to cause the data processing circuitry to: perform a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits, the bit-testing procedure comprising for each processed element of the plural elements: setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index.

2 . The apparatus as claimed in claim 1 , wherein the plural elements subjected to the bit-testing procedure comprise all elements of the source vector register.

3 . The apparatus as claimed in claim 1 , wherein in the bit-testing procedure an element of the plural elements is subjected to the bit-testing procedure as the processed element when a respective predicate bit of a set of governing predicate bit values has a first predetermined value.

4 . The apparatus as claimed in claim 3 , wherein a number of values in the set of governing predicate bit values matches a number of elements in the source vector register.

5 . The apparatus as claimed in claim 3 , wherein the bit-testing instruction specifies the set of governing predicate bit values.

6 . The apparatus as claimed in claim 5 , wherein the bit-testing instruction specifies a register holding the set of governing predicate bit values.

7 . The apparatus as claimed in claim 3 , wherein in the bit-testing procedure, when the respective predicate bit of the set of governing predicate bit values does not have the first predetermined value, the respective result bit of the plural result bits is set to a second predetermined value.

8 . The apparatus as claimed in claim 1 , wherein the data processing circuitry is arranged to store the plural result bits into a result register.

9 . The apparatus as claimed in claim 8 , wherein the result register is specified in the bit-testing instruction.

10 . The apparatus as claimed in claim 1 , wherein a count of the plural result bits matches a count of the plural elements stored in the source vector register.

11 . The apparatus as claimed in claim 1 , wherein in the bit-testing procedure the respective result bit of the plural result bits is set to match the value of the tested bit.

12 . The apparatus as claimed in claim 1 , wherein in the bit-testing procedure the respective result bit of the plural result bits is set not to match the value of the tested bit.

13 . The apparatus as claimed in claim 11 , wherein the instruction decoding circuitry is responsive to a further bit-testing instruction, which causes the data processing circuitry to perform a further bit-testing procedure comprising setting a further respective result bit of further plural result bits not to match a value of a further tested bit.

14 . The apparatus as claimed in claim 12 , wherein the instruction decoding circuitry is responsive to a further bit-testing instruction, which causes the data processing circuitry to perform a further bit-testing procedure comprising setting a further respective result bit of further plural result bits to match a value of a further tested bit.

15 . The apparatus as claimed in claim 1 , wherein the index is an immediate value in the bit-testing instruction.

16 . The apparatus as claimed in claim 1 , wherein the index is a scalar value stored in a scalar index register specified in the bit-testing instruction.

17 . The apparatus as claimed in claim 1 , wherein the bit-testing instruction specifies a vector index register holding plural index values, and in the bit-testing procedure, for each processed element of the plural elements, the index is given by a respective index value of the plural index values.

18 . An method of operating a data processing apparatus comprising:
decoding instructions and generating control signals in dependence on the instructions; performing data processing operations in response to the control signals generated; and in response to a bit-testing instruction specifying a source vector register and an index causing performance of a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits, wherein the bit-testing procedure comprises for each processed element of the plural elements: setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index.

19 . (canceled)

20 . A computer program for controlling a host data processing apparatus to provide an instruction execution environment comprising:
instruction decoding program logic to decode instructions and generate control signals in dependence on the instructions; and data processing program logic to perform data processing operations in response to the control signals generated by the instruction decoding program logic, wherein the instruction decoding program logic is responsive to a bit-testing instruction specifying a source vector data structure and an index to cause the data processing program logic to: perform a bit-testing procedure on plural elements stored in the source vector data structure to generate plural result bits, the bit-testing procedure comprising for each processed element of the plural elements: setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector data structure indicated by the index.

21 . A computer-readable storage medium storing in a non-transient fashion the computer program according to claim 20 .

Assignees

• Advanced Risc Mach Ltd

Inventors

• Magklis Grigorios
• Stephens Nigel John

Classifications

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F9/30038 Primary

  using a mask · CPC title

• G06F9/30018 Primary

  Bit or string instructions · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title