Method of manufacturing MRAM device with enhanced etch control

Patent metadata

Field	Value
Publication number	US-12274176-B2
Application number	US-202318230358-A
Country	US
Kind code	B2
Filing date	Aug 4, 2023
Priority date	Apr 22, 2020
Publication date	Apr 8, 2025
Grant date	Apr 8, 2025

Abstract

A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

First claim

The invention claimed is:

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, the substrate comprising a logic region and a memory region;
depositing a bottom electrode layer across the logic region and the memory region;
depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer;
depositing a sacrificial layer over the MTJ layer;
etching and removing the sacrificial layer in the memory region to expose the MTJ layer in the memory region, while keeping the MTJ layer in the logic region covered;
depositing a first conductive layer in the memory region and the logic region after etching the sacrificial layer such that the first conductive layer is in contact with the MTJ layer in the memory region and the sacrificial layer separates the MTJ layer from the first conductive layer in the logic region;
patterning the first conductive layer to expose the MTJ layer in the memory region; and
patterning the MTJ layer and the bottom electrode layer using the patterned first conductive layer as an etching mask to form a MTJ cell structure in the memory region.

2. The method according to claim 1 , further comprising, prior to the depositing of the bottom electrode layer:
forming a metal line layer having a metal line;
depositing a first dielectric layer in the memory region and the logic region over the metal line layer; and
forming a bottom electrode via within the first dielectric layer in the memory region.

3. The method according to claim 2 , wherein during the MTJ layer and the bottom electrode layer being patterned in the memory region, a thickness of the first conductive layer is reduced.

4. The method according to claim 3 , wherein the metal line is covered by the first dielectric layer in the logic region upon completion of patterning the MTJ layer and the bottom electrode layer.

5. The method according to claim 1 , wherein patterning the first conductive layer to expose the MTJ layer in the memory region comprises removing the first conductive layer in the logic region.

6. The method according to claim 1 , further comprising depositing a mask layer over the first conductive layer, wherein patterning the first conductive layer to expose the MTJ layer in the memory region comprises patterning the mask layer, and wherein the first conductive layer is patterned using the patterned mask layer as an etch mask.

7. The method according to claim 6 , wherein the mask layer comprises a same material as a material in the sacrificial layer.

8. The method according to claim 6 , wherein the patterning the MTJ layer and the bottom electrode layer in the memory region comprises performing an ion bombardment etching to remove an entirety of the mask layer and a portion of the first conductive layer in the memory region.

9. The method according to claim 8 , wherein the ion bombardment etching etches the MTJ layer using at least the first conductive layer as an etch mask to form the MTJ structure in the memory region.

10. The method according to claim 9 , wherein the ion bombardment etching further etches the bottom electrode layer using the first conductive layer as an etch mask to form a cell bottom electrode.

11. The method according to claim 8 , wherein the ion bombardment etching removes the mask layer and the first conductive layer in the logic region.

12. The method according to claim 1 , further comprising forming a spacer laterally surrounding sidewalls of the MTJ structure.

13. A method of manufacturing a semiconductor device, comprising:
forming a substrate, the substrate comprising a logic region and a memory region;
depositing a bottom electrode layer and a magnetic tunnel junction (MTJ) layer over the substrate;
depositing an etch buffer layer over the MTJ layer;
etching and removing the etch buffer layer in the memory region to expose the MTJ layer in the memory region, while keeping the MTJ layer in the logic region covered;
depositing a first conductive layer over the MTJ layer in the memory region and over the etch buffer layer in the logic region after etching the etch buffer layer such that the first conductive layer is in contact with the MTJ layer in the memory region and the etch buffer layer separates the MTJ layer from the first conductive layer in the logic region;
depositing a mask layer over the first conductive layer;
patterning the mask layer to form a pattern of a top electrode in the memory region;
patterning the first conductive layer by transferring the pattern to the first conductive layer in the memory region; and
etching the mask layer, the patterned first conductive layer, the MTJ layer and the bottom electrode layer using an etching operation to form the top electrode, an MTJ and a bottom electrode in the memory region.

14. The method according to claim 13 , wherein patterning the first conductive layer comprises removing the first conductive layer in the logic region.

15. The method according to claim 13 , wherein the first conductive layer as deposited is thicker than the bottom electrode layer.

16. The method according to claim 13 , wherein the etch buffer layer is made of a dielectric material.

17. The method according to claim 13 , further comprising, prior to the depositing of the bottom electrode layer:
forming a dielectric layer across the memory region and the logic region over the substrate; and
forming a bottom electrode via within the dielectric layer, wherein the bottom electrode layer is electrically connected to the bottom electrode via,
wherein the etching operation stops at the dielectric layer in the memory region while removing a thickness of the dielectric layer in the logic region.

18. The method according to claim 17 , wherein the dielectric layer comprises a layer stack comprising an inter-metallic dielectric layer, and the method further comprises:
completely removing the inter-metallic dielectric layer in the logic region subsequent to the etching operation.

19. A method of manufacturing a semiconductor device, comprising:
providing a substrate, the substrate comprising a logic region and a memory region;
forming a bottom electrode layer across the logic region and the memory region;
forming a magnetic tunnel junction (MTJ) layer over the bottom electrode layer;
forming an etch buffer layer over the MTJ layer;
etching and removing the etch buffer layer in the memory region to expose the MTJ layer in the memory region, while keeping the MTJ layer in the logic region covered;
forming a first conductive layer in the memory region and the logic region after etching the etch buffer layer such that first conductive layer is in contact with the MTJ layer in the memory region and the etch buffer layer separates the MTJ layer from the first conductive layer in the logic region;
etching the first conductive layer to expose the MTJ layer in the memory region; and
etching the first conductive layer, the MTJ layer and the bottom electrode layer to obtain a magnetoresistive random access memory structure including a bottom electrode, an MTJ, and a top electrode having a trapezoid shape,
wherein a longer parallel side of the trapezoid is the bottom electrode and a shorter parallel side of the trapezoid is the top electrode.

20. The method according to claim 19 , further comprising forming a spacer laterally surrounding sidewalls of the top electrode, the MTJ, and the bottom electrode.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chien Yu-Jen
• Wu Jung-Tang
• Wu Szu-Hua
• Lee Chin-Szu
• Wu Meng-Yu

Classifications

• H10N50/80

  Constructional details · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title

• H10N50/85

  Materials of the active region · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title