Enhanced base die heat path using through-silicon vias

Patent metadata

Field	Value
Publication number	US-12266589-B2
Application number	US-202418635894-A
Country	US
Kind code	B2
Filing date	Apr 15, 2024
Priority date	Feb 19, 2020
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

First claim

What is claimed is:

1. A stacked die package, comprising:
a substrate;
a base die coupled to the substrate by solder;
a top die vertically over the base die, the top die coupled to the base die with interconnects, the top die having a first sidewall and a second sidewall, the second sidewall laterally opposite the first sidewall;
a first dummy die laterally spaced apart from the first sidewall of the top die, the first dummy die vertically over the base die, and the first dummy die comprising silicon;
a second dummy die laterally spaced apart from the second sidewall of the top die, the second dummy die vertically over the base die, and the second dummy die comprising silicon; and
an interface material layer continuous over and directly on the top die, the first dummy die and the second dummy die.

2. The stacked die package of claim 1 , wherein the interface material layer extends laterally beyond the base die.

3. The stacked die package of claim 1 , wherein the interface material layer extends laterally beyond the first dummy die and the second dummy die.

4. The stacked die package of claim 1 , further comprising:
a heat spreader over the interface material layer.

5. The stacked die package of claim 4 , wherein the heat spreader is further laterally spaced apart from a side of the first dummy die and laterally spaced apart from a side of the second dummy die.

6. The stacked die package of claim 1 , wherein the top die, the first dummy die and the second dummy die are within a footprint of the base die.

7. The stacked die package of claim 1 , wherein the first dummy die and the second dummy die include through silicon vias.

8. The stacked die package of claim 1 , wherein the first dummy die and the second dummy die route thermal energy from the base die away from the top die.

9. A stacked die package, comprising:
a substrate;
a first thermal energy generating die coupled to the substrate by solder;
a second thermal energy generating die vertically over the first thermal energy generating die, the second thermal energy generating die coupled to the first thermal energy generating die with interconnects, the second thermal energy generating die having a first sidewall and a second sidewall, the second sidewall laterally opposite the first sidewall;
a first die laterally spaced apart from the first sidewall of the second thermal energy generating die, the first die vertically over the first thermal energy generating die, and the first die comprising silicon;
a second die laterally spaced apart from the second sidewall of the second thermal energy generating die, the second die vertically over the first thermal energy generating die, and the second die comprising silicon; and
an interface material layer continuous over and directly on the second thermal energy generating die, the first die and the second die.

10. The stacked die package of claim 9 , wherein the interface material layer extends laterally beyond the first thermal energy generating die.

11. The stacked die package of claim 9 , wherein the interface material layer extends laterally beyond the first die and the second die.

12. The stacked die package of claim 9 , further comprising:
a heat spreader over the interface material layer.

13. A method of fabricating a stacked die package, the method comprising:
coupling a base die coupled to a substrate by solder;
coupling a top die to the base die with interconnects, the top die vertically over the base die, the top die having a first sidewall and a second sidewall, the second sidewall laterally opposite the first sidewall;
providing a first dummy die laterally spaced apart from the first sidewall of the top die, the first dummy die vertically over the base die, and the first dummy die comprising silicon;
providing a second dummy die laterally spaced apart from the second sidewall of the top die, the second dummy die vertically over the base die, and the second dummy die comprising silicon; and
forming an interface material layer continuous over and directly on the top die, the first dummy die and the second dummy die.

14. The method of claim 13 , wherein the interface material layer extends laterally beyond the base die.

15. The method of claim 13 , wherein the interface material layer extends laterally beyond the first dummy die and the second dummy die.

16. The method of claim 13 , further comprising:
forming a heat spreader over the interface material layer.

17. The method of claim 16 , wherein the heat spreader is further laterally spaced apart from a side of the first dummy die and laterally spaced apart from a side of the second dummy die.

18. The method of claim 13 , wherein the top die, the first dummy die and the second dummy die are within a footprint of the base die.

19. The method of claim 13 , wherein the first dummy die and the second dummy die include through silicon vias.

20. The method of claim 13 , wherein the first dummy die and the second dummy die route thermal energy from the base die away from the top die.

Assignees

• Intel Corp

Inventors

• Bertrand Weston
• Arrington Kyle
• Devasenathipathy Shankar
• Mccann Aaron
• Neal Nicholas
• Wan Zhimin

Classifications

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W40/22 Primary

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title