NAND flash memory and reading method thereof

Patent metadata

Field	Value
Publication number	US-9564236-B2
Application number	US-201514876828-A
Country	US
Kind code	B2
Filing date	Oct 7, 2015
Priority date	Dec 8, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

The disclosure provides a NAND flash memory and a reading method thereof, which may read a negative threshold value of a memory cell without using a negative-voltage-generating circuit. The disclosed NAND flash memory includes a sense amplifier, a bit line selecting circuit and an array having a plurality of NAND string units. The disclosed NAND flash memory includes a ΔV supplying portion element that applies a positive voltage to a source line, a P well formed with a selected memory cell, and a non-selected bit line which is adjacent to a selected bit line, within a predetermined time period, after the selected bit line is pre-charged and during a reading process.

First claim

What is claimed is:

1. A reading method of a NAND flash memory comprising:
applying a pre-charge voltage to a selected bit line;
applying a voltage for determining a threshold value of a memory cell to a selected word line;
applying a voltage capable of turning on the memory cell regardless of a status of the memory cell to a non-selected word line;
detecting a voltage of the selected bit line after discharging the selected bit line by electrical coupling the pre-charged selected bit line to a source line; and
after pre-charging the selected bit line, applying a same positive voltage to the source line, a P-well formed with a selected memory cell and a non-selected bit line adjacent to the selected bit lines within a predetermined time period.

2. The reading method of the NAND flash memory as recited in claim 1 , further comprising:
discharging the selected bit line started after applying the positive voltage, and wherein the step of applying the positive voltage is stopped before detecting the voltage of the selected bit line.

3. The reading method of the NAND flash memory as recited in claim 1 , wherein the positive voltage is set according to a negative threshold value of the memory cell that is to be read.

4. The reading method of the NAND flash memory as recited in claim 1 , wherein the step of applying the positive voltage comprises:
shorting out the source line, the P-well and the non-selected bit line; and
simultaneously applying the positive voltage to the source line, the P-well and the non-selected bit line.

5. The reading method of the NAND flash memory as recited in claim 1 , wherein the step of applying the positive voltage comprises:
turning on a plurality of transistors respectively connected with the source line, the P-well and the non-selected bit line, such that the source line, the P-well and the non-selected bit line are connected in parallel; and
applying the positive voltage to the transistors.

6. The reading method of the NAND flash memory as recited in claim 1 , wherein when the selected bit line is an odd-numbered bit line, the non-selected bit line is an even-numbered bit line, and when the selected bit line is an even-numbered bit line, the non-selected bit line is an odd-numbered bit line.

7. The reading method of the NAND flash memory as recited in claim 1 , wherein the reading method of the NAND flash memory is executed for verifying a lower limit value of a negative threshold value distribution at erasing.

8. The reading method of the NAND flash memory as recited in claim 7 , wherein the reading method of the NAND flash memory is executed after verifying an upper limit value of the negative threshold value distribution at erasing.

9. The reading method of the NAND flash memory as recited in claim 8 , wherein if the upper limit value of the threshold value of the data “1” of the erasing cell is above the predetermined value, then it is determined as unqualified, and then an erasing pulse that adds ΔV to the voltage of the previous erasing pulse is generated and applied to a selected block including the selected memory cell.

Assignees

• Winbond Electronics Corp

Inventors

• Suito Katsutoshi

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title