High density ferroelectric random access memory (FeRAM) devices and methods of fabrication

Patent metadata

Field	Value
Publication number	US-12262543-B1
Application number	US-202318450499-A
Country	US
Kind code	B1
Filing date	Aug 16, 2023
Priority date	Aug 6, 2021
Publication date	Mar 25, 2025
Grant date	Mar 25, 2025

Abstract

Non lead-based perovskite ferroelectric devices for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

First claim

What is claimed is:

1. A device structure comprising:
a plurality of memory devices laterally spaced apart, wherein individual ones of the plurality of memory devices comprise:
a first conductive layer comprising a first non-Pb based perovskite metal oxide, the first conductive layer comprising a first sidewall having a first slope;
a dielectric layer comprising a non-Pb based perovskite material on the first conductive layer, the dielectric layer comprising a second sidewall having a second slope; and
a second conductive layer comprising a second non-Pb based perovskite metal oxide on the dielectric layer, the second conductive layer comprising a third sidewall having a third slope, wherein the first slope, the second slope, and the third slope are measured relative to a normal to a lowermost surface of the first conductive layer, wherein the first slope comprises a first angle, the second slope comprises a second angle and the third slope comprises a third angle, wherein the third angle is less than the second angle, and wherein the second angle is less than the first angle, and wherein the first slope, the second slope, and the third slope are each greater than or equal to zero degrees.

2. The device structure of claim 1 , wherein the first angle and the third angle are between 0 and 10 degrees.

3. The device structure of claim 1 , wherein the first angle, the second angle, and the third angle are each between 0 degrees and 30 degrees.

4. The device structure of claim 1 , wherein a first device in the plurality of memory devices is laterally separated from a second device in the plurality of memory devices by a spacing, and wherein the first device and the second device each comprise a same height, and wherein a ratio of height to spacing ranges between 1:2 and 5:1.

5. The device structure of claim 1 , wherein the first non-Pb based perovskite metal oxide comprises one of: La—Sr—CoO 3 , SrRuO 3 , La—Sr—MnO 3 , YBa 2 Cu 3 O 7 , Bi 2 Sr 2 CaCu 2 O 8 , or LaNiO and wherein the second non-Pb based perovskite metal oxide comprises one of: La—Sr—CoO 3 , SrRuO 3 , La—Sr—MnO 3 , YBa 2 Cu 3 O 7 , Bi 2 Sr 2 CaCu 2 O 8 , or LaNiO 3 .

6. The device structure of claim 1 , wherein the dielectric layer comprises one of:
a perovskite material which includes one of: BaTiO 3 , KNbO 3 , or NaTaO 3 ;
bismuth ferrite (BFO), or BFO doped with an element from 3d, 4d, 5d, 6d, 4f, or 5f series of periodic table;
a relaxor ferroelectric material which includes one of: barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a first hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
a second hexagonal ferroelectric of a type h-RMnO 3 , wherein R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxide of a form Hf 1-x E x O z , where ‘x’ denotes a fraction, and E includes one of Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y;
ABO 3 niobate type compounds including LiNbO 3 , LiTaO 3 , LiTaO 2 F 2 , Sr x Ba 1-x Nb 2 O 6 where 0.32≤x≤0.8, or KSr 2 Nb 5 O 15 ; or
an improper ferroelectric material which comprises an epitaxial bilayer stack including one of: [barium titanate/strontium titanate]n or [lanthanum aluminate/strontium titanate]n, wherein ‘n’ represents a number of bilayers, and wherein ‘n’ is between 1 and 100.

7. The device structure of claim 1 , further comprising:
a third conductive layer below the first conductive layer, the third conductive layer comprising a fourth sidewall, the fourth sidewall comprising a fourth angle; and
a fourth conductive layer above the second conductive layer, the fourth conductive layer comprising a fifth sidewall, the fifth sidewall comprising a fifth angle, wherein the third conductive layer comprises one of: La—Sr—CoO 3 , SrRuO 3 , La—Sr—MnO 3 , YBa 2 Cu 3 O 7 , Bi 2 Sr 2 CaCu 2 O 8 , or LaNiO 3 , and wherein the fourth conductive layer comprises one of: La—Sr—CoO 3 , SrRuO 3 , La—Sr—MnO 3 , YBa 2 Cu 3 O 7 , Bi 2 Sr 2 CaCu 2 O 8 , or LaNiO 3 .

8. The device structure of claim 7 , wherein the first angle, the second angle, the third angle, the fourth angle, and the fifth angle are each between 0 degrees and 30 degrees.

9. The device structure of claim 7 , wherein the fourth sidewall and the fifth sidewall are collinear.

10. A device structure comprising:
a plurality of memory devices laterally spaced apart, wherein individual ones of the plurality of memory devices comprise:
a first conductive layer comprising a non-Pb based perovskite metal oxide, the first conductive layer comprising a first sidewall having a first slope;
a dielectric layer comprising a non-linear polar material having a form ABB′O 3 , wherein B′ is a dopant for atomic site B, wherein O is oxygen, wherein the dielectric layer is on the first conductive layer, and wherein the dielectric layer comprises a second sidewall having a second slope; and
a second conductive layer comprising a second non-Pb based perovskite metal oxide on the dielectric layer, the second conductive layer comprising a third sidewall having a third slope, wherein the first slope, the second slope, and the third slope are measured relative to a normal to lowermost surface of the first conductive layer, wherein the first slope comprises a first angle, the second slope comprises a second angle and the third slope comprises a third angle, wherein the third angle is less than the second angle, and wherein the second angle is less than the first angle, and wherein the first slope, the second slope, and the third slope are each greater than or equal to zero degrees.

11. The device structure of claim 10 , wherein a first device in the plurality of memory devices is laterally separated from a second device in the plurality of memory devices by a spacing, wherein the first device and the second device each comprise a substantially equal height, wherein a ratio of height to the spacing is 1:1 or less, and wherein the height is between 7 nm and 90 nm, and wherein the spacing is between 20 nm and 50 nm.

12. The device structure of claim 10 , wherein “A” includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein “B” includes one of Zr, Al, Hf, Mn, Fe, Ta, or Nb, and wherein “B” includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn.

13. A device structure comprising:
a transistor comprising:
a source;
a gate; and
a drain; and

a memory device coupled with the drain of the transistor, the memory device comprising:
a bottom electrode comprising a first non-Pb based perovskite metal oxide, the bottom electrode comprising a first sidewall having a first slope;
a dielectric layer comprising a non-linear polar material having a form ABB′O 3 , AA′B′O 3 , or ABO 3 , wherein A′ is a first dopant for atomic site A, wherein B′ is a second dopant for atomic site B, wherein O is oxygen, wherein the dielectric layer is on the bottom electrode, and wherein the dielectric layer comprises a second sidewall having a second slope; and
a top electrode comprising a second non-Pb based perovskite metal oxide on the dielectric layer, the bottom electrode comprising a third sidewall having a third slope, wherein the first slope, the second slope, and the third slope are measured relative to a normal to a lowermost

Assignees

• Kepler Computing Inc

Inventors

• Guhabiswas Debraj
• Perez Maria Isabel
• Wu Jason Y
• Clarkson James David
• Velarde Gabriel Antonio Paulius
• Mukherjee Niloy
• Sato Noriyuki
• Mathuriya Amrita
• Manipatruni Saskikanth
• Ramesh Ramamoorthy

Classifications

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/694

  comprising noble metals or noble metal oxides · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title

• H10B53/30 Primary

  characterised by the memory core region · CPC title