Trench capacitors with shared electrode

Patent metadata

Field	Value
Publication number	US-12262541-B1
Application number	US-202217655419-A
Country	US
Kind code	B1
Filing date	Mar 18, 2022
Priority date	Mar 15, 2022
Publication date	Mar 25, 2025
Grant date	Mar 25, 2025

Abstract

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

First claim

What is claimed is:

1. A device, comprising:
a first region comprising:
a first conductive interconnect within a first dielectric in a first level, the first conductive interconnect comprising a first lateral thickness; and
a second level above the first level, the second level comprising:
an electrode structure on the first conductive interconnect, the electrode structure comprising a first conductive hydrogen barrier layer and a first conductive fill material, wherein the electrode structure comprises a second lateral thickness;
an etch stop layer laterally surrounding the electrode structure;
a plate electrode on the electrode structure, the plate electrode extending beyond a perimeter of the electrode structure and on the etch stop layer;
a second dielectric on the plate electrode and on the etch stop layer;
a plurality of trenches within the second dielectric;
a plurality of trench capacitors on the plate electrode, wherein individual ones of the plurality of trench capacitors is in individual ones of the plurality of trenches, and wherein the individual ones of the plurality of trench capacitors comprise:
a dielectric spacer along a sidewall of the individual ones of the plurality of trenches;
a first electrode on a base and on the dielectric spacer along the sidewall of the individual ones of the plurality of trenches, wherein the first electrode is in contact with the plate electrode;
a dielectric layer comprising a ferroelectric material or a paraelectric material substantially conformal to the first electrode; and
a second electrode in contact with the dielectric layer; and

a plurality of via electrodes wherein, individual ones of the plurality of via electrodes is on the second electrode of the individual ones of the plurality of trench capacitors, wherein the individual ones of the plurality of via electrodes comprise:
a second conductive hydrogen barrier layer comprising a lateral portion in contact with the second electrode and substantially vertical portions connected to the lateral portion; and
a second conductive fill material adjacent to the second conductive hydrogen barrier layer; and

a second region adjacent to the first region, the second region comprising:
a second conductive interconnect within the first dielectric in the first level and wherein the second level further comprises:
a metal structure; and
a via structure coupled between the second conductive interconnect and the metal structure, wherein at least a first portion of the via structure is adjacent to the etch stop layer, and a second portion of the via structure is adjacent to the second dielectric.

2. The device of claim 1 , wherein the plate electrode extends beyond a perimeter of the individual ones of the plurality of trench capacitors.

3. The device of claim 1 , further comprising a third dielectric on the second dielectric and portions of the individual ones of the plurality of trench capacitors, wherein the third dielectric comprises a material having 90% of theoretical material density such as but not limited to Al x O y , HfO x , AlSiO x , ZrO x , TiO x , AlSiO X , HfSiO X , TaSiO X , AlN, ZrN, HfN, or SiN.

4. The device of claim 3 , wherein the metal structure and the plurality of via electrodes are laterally surrounded by the third dielectric.

5. The device of claim 1 , wherein the individual ones of the plurality of trench capacitors are spaced apart by a distance between at least 10 nm.

6. The device of claim 1 , wherein the electrode structure is directly below a trench capacitor in the plurality of trench capacitors.

7. The device of claim 1 , wherein the first region further comprises a third conductive interconnect on a same level as the first conductive interconnect, and wherein the third conductive interconnect is at least partially below the plate electrode but not coupled with the plate electrode.

8. The device of claim 1 , wherein the plate electrode comprises:
a third portion that extends along a first direction on a first plane;
a fourth portion that extends parallel to the first direction, the fourth portion on a second plane, the second plane behind the first plane; and
a fifth portion that extends orthogonally from the third portion to the fourth portion.

9. The device of claim 8 , wherein the third portion is connected to a first midpoint of the third portion to a second midpoint of the fourth portion.

10. The device of claim 9 , wherein the plate electrode comprises:
a first pair of trench capacitors in the plurality of trench capacitors on the third portion;
a second pair of trench capacitors in the plurality of trench capacitors on the fourth portion; and
at least one trench capacitor in the plurality of trench capacitors on the fifth portion.

11. The device of claim 1 , wherein the second lateral thickness is less than the first lateral thickness.

12. The device of claim 1 , wherein the dielectric layer comprises:
bismuth ferrite (BFO) or BFO with a first doping material, where in the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ;
a hexagonal ferroelectric which includes one of: YMnO 3 , or LuFeO 3 ;
hexagonal ferroelectrics of a type h-RMnO 3 , where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);

hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides or their alloyed oxides; hafnium oxides such as Hf (1 -x)E x O y , where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, where x and y are first and second fractions, respectively;
Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-x-y) Mg (x) Nb (y) N, where x and y are third and fourth fractions, respectively
y doped HfO 2 , where y includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; or
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100; or

a paraelectric material comprising SrTiO 3 , Ba (x) Sr (y) TiO 3 (where x is −0.05, and y is 0.95), HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or a PMN-PT based relaxor ferroelectrics.

13. The device of claim 1 , wherein the first conductive hydrogen barrier layer is between the first conductive interconnect and the first conductive fill material, and wherein the first conductive hydrogen barrier layer and the second conductive hydrogen barrier layer comprise TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N 2 , TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti 2 O, WO 3 , SnO 2 , ITO, IGZO, ZO, or METGLAS series of alloys.

14. The device of claim 1 , wherein the dielectric

Assignees

• Kepler Computing Inc

Inventors

• Sato Noriyuki
• Gosavi Tanay
• Rios Rafael
• Mathuriya Amrita
• Mukherjee Niloy
• Manfrini Mauricio
• Dokania Rajeev Kumar
• Rathi Somilkumar J
• Manipatruni Sasikanth

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/711

  having non-planar surfaces, e.g. formed by texturisation · CPC title

• H10N79/00

  Integrated devices, or assemblies of multiple devices, comprising at least one solid-state element covered by group H10N70/00 (ReRAM devices H10B63/00; PCRAM devices H10B63/10) · CPC title