Bonding process for forming semiconductor device structure

Patent metadata

Field	Value
Publication number	US-12258265-B2
Application number	US-202318354012-A
Country	US
Kind code	B2
Filing date	Jul 18, 2023
Priority date	Nov 29, 2017
Publication date	Mar 25, 2025
Grant date	Mar 25, 2025

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

First claim

What is claimed is:

1. A semiconductor device structure, comprising:
a first substrate comprising a first face, a second face opposite the first face, and one or more movable microelectromechanical system (MEMS) devices between the first face and second face;
a second substrate bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate; and
one or more expansion joints in the second face of the first substrate.

2. The semiconductor device structure of claim 1 , wherein the one or more expansion joints substantially corresponds to an outer perimeter of the first substrate.

3. The semiconductor device structure of claim 1 , wherein a first expansion joint of the one or more expansion joints extends in a first direction substantially parallel to an outer edge of the first substrate.

4. The semiconductor device structure of claim 3 , wherein a second expansion joint of the one or more expansion joints intersects the first expansion joint.

5. The semiconductor device structure of claim 4 , wherein the first expansion joint and the second expansion joint are perpendicular to one another.

6. The semiconductor device structure of claim 4 , wherein the first expansion joint and the second expansion joint bisect one another.

7. The semiconductor device structure of claim 1 , wherein the one or more expansion joints includes a first expansion joint having a first pair of distal ends, wherein a first end of the first pair of distal ends is spaced apart from an outer perimeter of the first substrate.

8. The semiconductor device structure of claim 7 , wherein the one or more expansion joints includes a second expansion joint having a second pair of distal ends, wherein a second end of the second pair of distal ends is spaced apart from the outer perimeter of the first substrate.

9. The semiconductor device structure of claim 8 , wherein the first expansion joint traverses the second expansion joint.

10. The semiconductor device structure of claim 8 , wherein the first expansion joint bisects the second expansion joint.

11. A semiconductor device structure, comprising:
a first die comprising a first face and a second face opposite the first face;
a second die bonded to the first face of the first die such that the second face of the first die faces away from the second die; and
one or more expansion trenches in the second face of the first die, wherein a expansion trench has sidewalls that extend linearly along the second face of the first die and that terminate at a bottom surface of the expansion trench, the bottom surface being disposed at a depth between the first face and the second face of the first die.

12. The semiconductor device structure of claim 11 , wherein the first die does not comprise any transistor.

13. The semiconductor device structure of claim 11 , wherein the second die comprises complementary metal oxide semiconductor (CMOS) transistors.

14. The semiconductor device structure of claim 13 , wherein the first die comprises a plurality of movable elements.

15. The semiconductor device structure of claim 11 , wherein the one or more expansion trenches comprises:
a first linear expansion trench that extends in parallel with a first sidewall of the first die; and
a second linear expansion trench that extends in parallel with a second sidewall of the first die such that the second linear expansion trench perpendicularly intersects the first linear expansion trench in the second face of the first die.

16. The semiconductor device structure of claim 15 , wherein the first linear expansion trench and the second linear expansion trench have the same length as one another.

17. A semiconductor device structure, comprising:
a first die comprising a first face and a second face opposite the first face, the first die including a base layer defining the first face and a semiconductor layer defining the second face, wherein a material layer separates the base layer from the semiconductor layer, and wherein first bonding structures are disposed on the semiconductor layer;
a second die including a substrate and an interconnect layer disposed over the substrate, wherein the interconnect layer includes second bonding structures that are bonded to the first bonding structures such that the second face of the first die faces away from the second die; and
one or more trenches in the base layer of the first die, wherein a trench has sidewalls that extend linearly along the second face of the first die and that terminate at a bottom surface of the trench, the bottom surface of the trench being disposed at a depth within the base layer.

18. The semiconductor device structure of claim 17 , wherein the material layer comprises a nitride or a carbide.

19. The semiconductor device structure of claim 17 , wherein the base layer comprises a semiconductor material or a dielectric material.

20. The semiconductor device structure of claim 17 , wherein the sidewalls of the trench extend in parallel with one another.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Chih-Hang
• Wang I-Shi
• Liu Jen-Hao

Classifications

• B81C3/005

  Passive alignment, i.e. without a detection of the position of the elements or using only structural arrangements or thermodynamic forces · CPC title

• B81C1/00888 Primary

  Multistep processes involving only mechanical separation, e.g. grooving followed by cleaving · CPC title

• B81C1/00269

  Bonding of solid lids or wafers to the substrate · CPC title

• B81C2201/0143

  Focussed beam, i.e. laser, ion or e-beam · CPC title

• B81C2201/013

  Etching · CPC title