Electronic devices in semiconductor package cavities

Patent metadata

Field	Value
Publication number	US-12255115-B2
Application number	US-202418617517-A
Country	US
Kind code	B2
Filing date	Mar 26, 2024
Priority date	Aug 24, 2020
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a semiconductor die attached to a die pad;
a mold compound covering the semiconductor die, the mold compound including a cavity;
a first conductive terminal proximate to a periphery of the semiconductor die, the first conductive terminal electrically connected to a lead of the semiconductor package;
a second conductive terminal extending from the semiconductor die through the mold compound into the cavity; and
a dielectric layer covering portions of the first conductive terminal and the second conductive terminal.

2. The semiconductor package of claim 1 , wherein the conductive terminal extends into the cavity via a bottom surface of the cavity, and wherein the cavity is uncovered.

3. The semiconductor package of claim 1 , wherein the first conductive terminal comprises a seed layer, a metal layer on the seed layer and a plating layer on the seed layer.

4. The semiconductor package of claim 1 , wherein the second conductive terminal comprises a seed layer, a metal layer on the seed layer, a metal post on the metal layer, and a plating layer on the metal post.

5. The semiconductor package of claim 4 , wherein the mold compound contacts a portion of the metal post.

6. The semiconductor package of claim 4 , wherein the dielectric layer contacts portions of the seed layer and the metal layer of the second conductive terminal.

7. The semiconductor package of claim 4 , wherein the plating layer includes tin silver.

8. The semiconductor package of claim 3 , wherein the dielectric layer contacts portions of the seed layer, the metal layer, and the plating layer of the first conductive terminal.

9. The semiconductor package of claim 1 , wherein the second conductive terminal is more proximate to a middle of the semiconductor die than the first conductive terminal.

10. The semiconductor package of claim 1 , wherein the first conductive terminal is electrically connected to the lead via a bond wire.

11. The semiconductor package of claim 1 , wherein the bond wire contacts the plating layer of the first conductive terminal.

12. The semiconductor package of claim 1 further comprising another semiconductor package within the cavity and electrically connected to the second conductive terminal.

13. The semiconductor package of claim 11 , wherein the another semiconductor package is a wafer chip scale package (WCSP).

14. The semiconductor package of claim 1 further comprising a passive electronic device within the cavity and electrically connected to the second conductive terminal.

15. A semiconductor package, comprising:
a semiconductor die attached to a die pad;
a mold compound covering the semiconductor die, the mold compound including a cavity;
a first conductive terminal along a periphery of the semiconductor die, the first conductive terminal electrically connected to a lead of the semiconductor package;
a second conductive terminal extending from the semiconductor die through the mold compound into the cavity, wherein the second conductive terminal includes solder; and
a dielectric layer covering portions of the first conductive terminal and the second conductive terminal.

16. The semiconductor package of claim 15 , wherein the first conductive terminal comprises a seed layer, a metal layer on the seed layer and a plating layer on the seed layer.

17. The semiconductor package of claim 15 , wherein the second conductive terminal comprises a seed layer, a metal layer on the seed layer, a plating layer on the metal layer, and solder on the plating layer.

18. The semiconductor package of claim 17 , wherein the mold compound contacts a portion of the solder.

19. The semiconductor package of claim 15 , wherein the second conductive terminal is more proximate to a middle of the semiconductor die than the first conductive terminal.

20. The semiconductor package of claim 15 further comprising another semiconductor package within the cavity and electrically connected to the second conductive terminal.

21. The semiconductor package of claim 11 , wherein the semiconductor package is a quad flat no leads (QFN) package.

Assignees

• Texas Instruments Inc

Inventors

• Manack Christopher Daniel
• Thompson Patrick Francis
• Chen Qiao

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/859

  Bump connectors and bond wires · CPC title