Multi-Vt nanosheet devices

Patent metadata

Field	Value
Publication number	US-12255106-B2
Application number	US-202117527355-A
Country	US
Kind code	B2
Filing date	Nov 16, 2021
Priority date	Nov 16, 2021
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.

First claim

The invention claimed is:

1. A method for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels, the method comprising:
forming a first set of nanosheet stacks having a first intersheet spacing;
forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing;
depositing a high-k (HK) layer within the first and second nanosheet stacks;
depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks;
depositing a dipole material; and
selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.

2. The method of claim 1 , wherein the material stack includes a first titanium nitride (TiN) layer, a zirconium oxide (ZrO) layer, and a second TiN layer.

3. The method of claim 2 , wherein the material stack selectively dopes the HK layer with zirconium (Zr) to decrease a crystallization temperature and creates the crystallized HK layer in the first set of nanosheet stacks with the first intersheet spacing.

4. The method of claim 1 , wherein the dipole material is lanthanum oxide (LaO).

5. The method of claim 1 , wherein a sacrificial layer and a capping layer are deposited after deposition of the dipole material to enable diffusion of the dipole material into the amorphous HK layer of the second set of nanosheet stacks.

6. The method of claim 5 , wherein the sacrificial layer is TiN and the capping layer is amorphous silicon (a-Si).

7. The method of claim 1 , further comprising depositing a gate metal over first and second nanosheet stacks.

8. A method for modulating threshold voltages for nanosheet stacks without patterning between nanosheet channels, the method comprising:
forming first nanosheet stacks having a first intersheet spacing;
forming second nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing;
constructing a crystallized high-k (HK) layer within the first nanosheet stacks;
constructing an amorphous high-k (HK) layer within the second nanosheet stacks;
depositing a dipole material; and
selectively diffusing the dipole material into the amorphous HK layer of the second nanosheet stacks to modulate the threshold voltages for the nanosheet stacks.

9. The method of claim 8 , further comprising depositing a material stack that, when annealed, creates the crystallized HK layer in the first nanosheet stacks and the amorphous HK layer in the second nanosheet stacks.

10. The method of claim 9 , wherein the material stack includes a first titanium nitride (TiN) layer, a zirconium oxide (ZrO) layer, and a second TiN layer.

11. The method of claim 10 , wherein the material stack selectively dopes the HK layer with zirconium (Zr) to decrease a crystallization temperature and creates the crystallized HK layer in the first nanosheet stacks with the first intersheet spacing.

12. The method of claim 8 , wherein the dipole material is lanthanum oxide (LaO).

13. The method of claim 8 , wherein a sacrificial layer and a capping layer are deposited after deposition of the dipole material to enable diffusion of the dipole material into the amorphous HK layer of the second nanosheet stacks.

14. The method of claim 13 , wherein the sacrificial layer is TiN and the capping layer is amorphous silicon (a-Si).

15. The method of claim 8 , further comprising depositing a gate metal over the first and second nanosheet stacks.

16. A semiconductor structure comprising:
first nanosheet stacks having a first intersheet spacing;
second nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing;
a crystallized high-k (HK) layer disposed within the first nanosheet stacks;
an amorphous high-k (HK) layer disposed within the second nanosheet stacks; and
a dipole material disposed within the first and second nanosheet stacks.

17. The semiconductor structure of claim 16 , wherein the dipole material is lanthanum oxide (LaO).

18. The semiconductor structure of claim 16 , wherein the crystallized HK layer includes a dopant to decrease a crystallization temperature.

19. The semiconductor structure of claim 18 , wherein the dopant is zirconium oxide (ZrO).

20. The semiconductor structure of claim 16 , wherein a gate metal directly contacts the crystallized HK layer within the first nanosheet stacks and the amorphous HK layer in the second nanosheet stacks.

Assignees

• IBM
• Interational Business Machines Corp

Inventors

• Zhang Jingyun
• Ando Takashi
• Lee Choonghyun
• Reznicek Alexander

Classifications

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title