Gate stack formed with interrupted deposition processes and laser annealing

Patent metadata

Field	Value
Publication number	US-9613866-B2
Application number	US-201615155474-A
Country	US
Kind code	B2
Filing date	May 16, 2016
Priority date	Jun 30, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.

First claim

What is claimed:

1. A method comprising a millisecond anneal to crystallize a lower portion of a high-k dielectric material with a top layer of the high-k dielectric material being amorphous, with restriction of a substrate preheat temperature during the millisecond anneal to below 600° C.

2. The method of claim 1 , wherein the millisecond anneal is a millisecond laser anneal.

3. The method of claim 1 , wherein the millisecond anneal is from 100 to 3000 microseconds measured at 100° C. below temperature peak value at a peak temperature range of from 1000° C. to 1250° C.

4. The method of claim 1 , further comprising depositing the high-k dielectric material in an interrupted atomic layer deposition (ALD) process with the millisecond anneal to crystallize the high-k dielectric material being performed during an interrupted cycle of the deposition of the high-k dielectric material.

5. The method of claim 4 , further comprising diffusing La or Mg atoms into the high-k dielectric bi-layer.

6. The method of claim 5 , further comprising creating multiple nFET transistors.

7. The method of claim 6 , wherein the La or Mg is provided over select transistors, diffusing La/Mg atoms through the high-k dielectric bi-layer.

8. The method of claim 1 , wherein the crystallizing of the lower portion of the high-k dielectric material is below 2 nm.

9. The method of claim 1 , wherein a thickness of the crystallized lower portion of the high-k dielectric material is less than 12 Å.

10. The method of claim 9 , wherein the high-k dielectric material contains La or Mg atoms.

11. The method of claim 10 , wherein an amount of atoms of the La or Mg atoms is larger than 1.5e14 atoms/cm 2 .

12. The method of claim 9 , further comprising forming multiple nFET transistors where at least one of the nFET transistors has the La or Mg atoms.

13. The method of claim 9 , wherein the La or Mg atoms will form dipoles by binding with oxygen.

Assignees

• IBM

Inventors

• Ando Takashi
• Dasgupta Aritra
• Gluschenkov Oleg
• Kannan Balaji
• Kwon Unoh

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P34/42

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/6544

  to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer · CPC title