Process for obtaining a nitride layer

Patent metadata

Field	Value
Publication number	US-12252807-B2
Application number	US-201816956374-A
Country	US
Kind code	B2
Filing date	Dec 24, 2018
Priority date	Dec 22, 2017
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

A process for obtaining a nitride (N) layer preferably obtained from at least one of gallium (Ga), indium (In) and aluminium (Al), may include: on a stack including a substrate and at least the following layers successively disposed from the substrate: a creep layer having a glass transition temperature, T glass transition , and a crystalline layer, forming pads by etching the stack so that each pad includes at least a creep segment formed by at least a portion of the creep layer, and a crystalline segment formed by the crystalline layer; and growing by epitaxy a crystallite on each of the pads and continuing the epitaxial growth of the crystallites so as to form the nitride layer. The epitaxial growth may be carried out at a temperature T epitaxy , such that T epitaxy ≥k1×T glass transition , with k1 being 0.8.

First claim

The invention claimed is:

1. A process for obtaining a nitride (N) layer optionally obtained from gallium (Ga), indium (In), and/or aluminum (Al), the process comprising:
on a stack comprising a substrate and, successively disposed from the substrate, a first layer, as a creep layer comprising a material having a glass transition temperature, T glass transition , and a second layer, as a crystalline layer, which is crystalline and different from the creep layer, forming pads by etching at least the crystalline layer and at least a portion of the creep layer so that: (i) each pad comprises: (i-a) a first segment, as a creep segment, formed by at least a portion of the creep layer; and (i-b) a second crystalline segment, as a crystalline segment, formed by the crystalline layer and surmounting the creep segment; and each pad comprises a section whose maximum dimension is in a range of from 10 to 500 nm; and
growing by epitaxy a crystallite on at least some of the pads and continuing the epitaxial growth of crystallites at least until coalescence of the crystallites carried by two adjacent pads, so as to form the nitride layer,
wherein the growing by epitaxy is carried out at a temperature T epitaxy , corresponding to formula (1):
T eptaxy ≥k 1 ×T glass transition   (1),

wherein k1≥0.8.

2. The process of claim 1 , wherein the creep layer comprises:
a silicon oxide Si x O y , x and y being integers;
a glass;
a borosilicate glass; or
a borophosphosilicate glass (BPSG).

3. The process of claim 1 , wherein k1≥1.

4. The process of claim 1 , wherein
T epitaxy ≥k 2× T melting min   (2),

wherein T melting min is a lowest melting temperature among melting temperatures of the segments forming the pad, and k2≤0.9.

5. The process of claim 1 , wherein the stack comprises, before the forming of the pads by etching, a priming layer, surmounting the crystalline layer,
wherein the priming layer comprises the same material as the nitride layer.

6. The process of claim 1 , wherein, prior to the forming, the stack comprises an elaborate substrate of silicon on insulator (SOI) type comprising a base substrate surmounted successively by an oxide layer forming the creep layer and a semiconductor layer forming the crystalline layer.

7. The process of claim 1 , wherein the creep segment has a height e 220 conforming to formula (3)
e 220 ≥0.1× d pad   (3),

wherein dpad is a diameter of the pad or more generally a distance edge to edge of the pad taken, at the creep segment and in a direction parallel to a main plane wherein the substrate extends.

8. The process of claim 1 , wherein the pads have a height H pad , and
wherein two adjacent pads are spaced by a distance D, conforming to formula (4):
H pad /D< 2  (4).

9. The process of claim 1 , wherein the crystalline layer comprises silicon.

10. The process of claim 1 , wherein the crystalline layer comprises SiC or Al 2 O 3 .

11. The process of claim 1 , wherein the forming of the pads comprises etching the crystalline layer and etching only a first portion of the creep layer so as to keep a second portion of the creep layer between the pads.

12. The process of claim 1 , wherein the forming of the pads is carried out so that
d crystallite /d pad ≥k 3  (5),

wherein k3=3, d pad is a maximum dimension of the section of the pad (taken in a direction parallel to a main plane wherein the substrate extends, d crystallite is a dimension of the crystallite measured in the same direction as d pad at a time of coalescence of the crystallites.

13. The process of claim 1 , wherein each pad has an upper face, and
wherein the growing by epitaxy of the crystallites takes place at least in part from the upper face.

14. The process of claim 1 , wherein the creep layer comprises SiO 2 .

15. The process of claim 1 , wherein growing by epitaxy the crystallite on at least some of the pads and continuing the epitaxial growth of crystallites at least until coalescence of the crystallites carried by two adjacent pads, so as to form the nitride layer comprises forming a void having bottom and side surfaces at least partially defined by the etched creep layer and a top surface at least partially defined by a bottom surface of the coalesced crystallites.

16. The process of claim 1 , wherein the pads comprise a buffer layer surmounting the crystalline layer, the buffer layer comprising a different material from that of the nitride layer.

17. The process of claim 16 , wherein the buffer layer is formed by epitaxy deposition on top of the crystalline layer, before the forming of the pads by etching.

18. The process of claim 16 , wherein the nitride layer is a gallium nitride layer (GaN), and
wherein the pads comprise, before the growing by epitaxy of the nitride layer, a priming layer, surmounting the buffer layer and comprising gallium nitride (GaN).

19. A microelectronic device, comprising:
a continuous nitride (N) layer formed using the process of claim 1 ;
the pads; and
the substrate surmounted by the plurality of pads,
wherein each pad comprises the first segment, as the creep segment, having the glass transition temperature, T glass transition , and the second crystalline segment formed of a crystalline material,
wherein the creep segment and the crystalline segment are successively disposed from the substrate,
wherein the continuous nitride (N) layer is entirely supported by the pads, and
wherein a creep segment material and a nitride layer material are selected so that:
T epitaxy > k 1×T glass transition ,

wherein k1>0.8, T epitaxy is a minimum temperature allowing formation of the nitride layer by epitaxy.

20. A light-emitting diode, comprising:
the device of claim 19 .

Assignees

• Commissariat Energie Atomique
• Centre Nat Rech Scient

Inventors

• Feuillet Guy
• Alloing Blandine
• Brandli Virginie
• Mathieu Benoit
• Zuniga Perez Jesus

Classifications

• H10H20/01335

  the light-emitting regions comprising nitride materials · CPC title

• H10H20/825

  containing nitrogen, e.g. GaN · CPC title

• H10H20/815

  having stress relaxation structures, e.g. buffer layers · CPC title

• C30B29/406

  Gallium nitride · CPC title

• C30B25/183 Primary

  being provided with a buffer layer, e.g. a lattice matching layer · CPC title