Sensor interposer employing castellated through-vias

Patent metadata

Field	Value
Publication number	US-12250768-B2
Application number	US-202318381074-A
Country	US
Kind code	B2
Filing date	Oct 17, 2023
Priority date	Feb 22, 2018
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

First claim

That which is claimed is:

1. A method of forming a sensor interposer comprising:
provide a planar substrate;
forming a plurality of through-vias in the planar substrate;
cutting a portion of the planar substrate to create an interposer substrate, the cutting comprising cutting through at least four of the through-vias to create at least four castellated through-vias;
forming a first electrical contact on the interposer substrate and electrically coupling the first electrical contact to a first castellated through-via;
forming a second electrical contact on the interposer substrate and electrically coupling the second electrical contact to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and
forming a guard trace on the interposer substrate, the guard trace electrically coupled between a third and a fourth through-via formed on the planar substrate, the guard trace isolating the first and second electrical contacts.

2. The method of claim 1 , wherein the guard trace comprises:
a first portion formed on a first surface of the interposer substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, and
a second portion formed on a second surface of the interposer substrate and electrically coupling the third castellated through-via to the fourth castellated through-via,
the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

3. The method of claim 1 , further comprising:
defining an opening in the interposer substrate between the first and second electrical contacts, and wherein the third castellated through-via is formed in a perimeter of the planar substrate, and the fourth castellated through-via is formed in a perimeter of the opening, and wherein the guard trace is a first guard trace; and
forming a second guard trace on the interposer substrate, the second guard trace having a first portion formed on the first surface of the interposer substrate and electrically coupling a fifth castellated through-via to a sixth castellated through-via, the second guard trace having a second portion formed on the second surface of the interposer substrate and electrically coupling the fifth castellated through-via to the sixth castellated through-via, the second guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts,
wherein the fifth castellated through-via is formed in a perimeter of the planar substrate, and the castellated sixth through-via is formed in a perimeter of the opening.

4. The method of claim 1 , further comprising electrically coupling a sensor wire to the first and second electrical contacts.

5. The method of claim 4 , wherein the sensor wire comprises a first wire material and a second wire material, the second wire material formed coaxially around the first wire material, a first portion of the first wire material extending beyond the second wire material at a first end of the sensor wire,
wherein electrically coupling the sensor wire comprises:
electrically coupling the first portion of the first wire material to the first electrical contact, and
electrically coupling the second wire materials to the second electrical contact.

6. The method of claim 1 , further comprising providing a printed circuit board (PCB) defining a surface feature, and the method further comprises engaging the surface feature with an opening defined in the planar substrate, the surface feature enabling alignment between the PCB and the sensor interposer.

7. The method of claim 4 , wherein the sensor wire includes a sensor chemical comprising glucose oxidase.

8. The method of claim 4 , wherein the sensor wire includes a sensor chemical configured to react with or more of glucose, lactate, or cholesterol.

9. The method of claim 4 , further comprising depositing a sensor chemical on a distal end of the sensor wire.

10. The method of claim 4 , wherein a controller is in communication with the sensor wire, the controller configured to receive sensor signals from the sensor wire, and determine an analyte concentration based on the sensor signals.

11. The method of claim 1 , wherein the first electrical contact and the second electrical contact are formed on opposite sides of the interposer substrate.

12. The method of claim 4 , wherein a distal end of the sensor wire is configured to be inserted into a wearer's skin.

Assignees

• Dexcom Inc

Inventors

• Frick Sean
• Jung Louis
• Lari David

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• A61B5/14532

  for measuring glucose, e.g. by tissue impedance measurement · CPC title

• H05K2201/0394

  Conductor crossing over a hole in the substrate or a gap between two separate substrate parts · CPC title

• H05K1/0219

  Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors · CPC title