Asymmetric NAND gate circuit, clock gating cell and integrated circuit including the same

Patent metadata

Field	Value
Publication number	US-12249993-B2
Application number	US-202318373017-A
Country	US
Kind code	B2
Filing date	Sep 26, 2023
Priority date	Oct 24, 2022
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

A clock gating cell is provided. The clock gating cell includes: an inverter circuit configured to generate an inverted clock signal by inverting a clock signal; a first control circuit configured to receive the inverted clock signal, an enable signal, and a scan enable signal, and output a first internal signal at a first node; a second control circuit configured to receive the first internal signal, the clock signal, the enable signal, and the scan enable signal, and output a second internal signal at a second node; and an output driver configured to receive the second internal signal, and output an output clock signal to an output node and a third internal signal to a third node. The first control circuit and the second control circuit are configured to receive the third internal signal at the third node.

First claim

What is claimed is:

1. A clock gating cell comprising:
an inverter circuit configured to generate an inverted clock signal by inverting a clock signal;
a first control circuit configured to receive the inverted clock signal, an enable signal, and a scan enable signal, and output a first internal signal at a first node;
a second control circuit configured to receive the first internal signal, the clock signal, the enable signal, and the scan enable signal, and output a second internal signal at a second node; and
an output driver configured to receive the second internal signal, and output an output clock signal to an output node and a third internal signal to a third node,
wherein the first control circuit and the second control circuit are configured to receive the third internal signal at the third node.

2. The clock gating cell of claim 1 , wherein the first control circuit comprises:
a first P-type transistor comprising a gate to which the scan enable signal is input;
a second P-type transistor comprising a gate to which the enable signal is input and a source connected to a drain of the first P-type transistor;
a third P-type transistor comprising a gate connected to the third node and a source connected to a drain of the second P-type transistor;
a fourth P-type transistor comprising a source to which a power supply voltage is applied and a drain connected to a drain of the third P-type transistor;
a fifth P-type transistor comprising a gate to which the inverted clock signal is input, a source connected to the drain of the third P-type transistor, and a drain connected to an internal node;
a first N-type transistor comprising a gate to which the inverted clock signal is input and a drain connected to the internal node;
a second N-type transistor comprising a gate connected to the third node and a drain connected to the internal node; and
a first inverter circuit comprising an input terminal connected to the internal node.

3. The clock gating cell of claim 2 , wherein a gate of the fourth P-type transistor and an output terminal of the first inverter circuit are connected to the first node to provide a feedback path for the first control circuit.

4. The clock gating cell of claim 1 , wherein the second control circuit comprises:
a first P-type transistor comprising a gate connected to the first node and a drain connected to the second node;
a second P-type transistor comprising a gate to which the clock signal is input and a drain connected to the second node;
a first N-type transistor, a second N-type transistor and a third N-type transistor that are connected to each other in parallel, each of the first N-type transistor, the second N-type transistor and the third N-type transistor comprising a drain connected to the second node;
a fourth N-type transistor comprising a gate to which the clock signal is input and a drain connected to a source of the first N-type transistor; and
a fifth N-type transistor comprising a gate connected to the first node and a drain connected to a source of the fourth N-type transistor.

5. The clock gating cell of claim 4 , wherein the first N-type transistor of the second control circuit comprises a gate to which the enable signal is input,
wherein the second N-type transistor of the second control circuit comprises a gate to which the scan enable signal is input,
wherein the third N-type transistor of the second control circuit comprises a gate connected to the third node.

6. The clock gating cell of claim 1 , wherein the output driver comprises:
a second inverter circuit having an input terminal connected to the second node, and configured to output the output clock signal at the output node; and
a third inverter circuit having an input terminal connected to the second node and an output terminal connected to the third node.

7. The clock gating cell of claim 1 , wherein the second control circuit comprises:
a first P-type transistor comprising a gate to which the clock signal is input and a drain connected to the second node;
a transmission gate circuit connected between the second node and a fourth node, and configured to be switched according to the clock signal and the inverted clock signal;
a first N-type transistor, a second N-type transistor and a third N-type transistor that are connected to each other in parallel, each of the first N-type transistor, the second N-type transistor and the third N-type transistor comprising a drain connected to the fourth node; and
a fourth N-type transistor comprising a gate connected to the first node and a drain connected to a source of the first N-type transistor.

8. The clock gating cell of claim 7 , wherein the transmission gate circuit comprises:
a second P-type transistor comprising a gate to which the inverted clock signal is input, a source connected to the second node, and a drain connected to the fourth node; and
a fifth N-type transistor comprising a gate to which the clock signal is input, a drain connected to the second node, and a source connected to the fourth node.

9. The clock gating cell of claim 7 , wherein the first N-type transistor comprises a gate to which the enable signal is input,
wherein the second N-type transistor comprises a gate to which the scan enable signal is input, and
wherein the third N-type transistor comprises a gate connected to the third node.

10. The clock gating cell of claim 7 , wherein the fourth node electrically connected to the first control circuit and the second control circuit.

11. An asymmetric NAND gate circuit comprising:
a first P-type transistor comprising a gate connected to a first node and a drain connected to a second node;
a second P-type transistor comprising a gate to which a clock signal is input and a drain connected to the second node;
a first N-type transistor, a second N-type transistor and a third N-type transistor that are connected to each other in parallel, each of the first N-type transistor, the second N-type transistor and the third N-type transistor comprising a drain connected to the second node;
a fourth N-type transistor comprising a gate to which the clock signal is input and a drain connected to a source of the first N-type transistor; and
a fifth N-type transistor comprising a gate connected to the first node and a drain connected to a source of the fourth N-type transistor.

12. The asymmetric NAND gate circuit of claim 11 , wherein the first N-type transistor comprises a gate to which an enable signal is input,
wherein the second N-type transistor comprises a gate to which a scan enable signal is input, and
wherein the third N-type transistor comprises a gate connected to a third node.

13. An integrated circuit comprising:
a first clock gating cell configured to receive a clock signal and output a first output clock signal according to a first enable signal; and
at least one first flip-flop configured to receive the first output clock signal,
wherein the first clock gating cell comprises:
an inverter circuit configured to invert the clock signal to generate an inverted clock signal;
a first control circuit configured to receive the inverted clock signal, the first enable signal and a scan enable signal, and output a first internal signal;
a second control circuit configured to receive the first internal signal, the clock signal, the first enable signal and the scan enable signal, and output a second internal signal; and
an output driver configured to receive the second internal signal and output the first output clock signal to an output node, and

wherein the output driver is configured to provide a third internal signal to the fir

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Byounggon
• Lee Dalhee

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• H03K3/037 Primary

  Bistable circuits · CPC title

• H03K19/0016 Primary

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title