Clock gating circuit that operates at high speed

Patent metadata

Field	Value
Publication number	US-9762240-B2
Application number	US-201615153799-A
Country	US
Kind code	B2
Filing date	May 13, 2016
Priority date	Jun 22, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.

First claim

What is claimed is:

1. A clock gating circuit comprising:
a first precharge unit configured to charge a first node based on a clock signal;
a second precharge unit configured to charge a second node based on the clock signal;
a first discharge unit configured to discharge the first node based on the clock signal;
a second discharge unit configured to discharge the second node based on the clock signal;
a first cross-coupled maintain unit configured to maintain the first node at a charge state according to a voltage level of the second node;
a second cross-coupled maintain unit configured to maintain the second node at the charge state according to a voltage level of the first node; and
a control unit configured to control the first and second discharge units to discharge the first node or the second node based on a clock enable signal,
wherein the control unit is configured to control the second discharge unit so that an output clock signal having a waveform corresponding to the clock signal is output at the second node during a specific time according to the clock enable signal.

2. The clock gating circuit of claim 1 , wherein in a case that the clock signal is a first level, the first and second precharge units are configured to charge the first and second nodes to a second level.

3. The clock gating circuit of claim 2 , wherein in a case that the clock signal is the second level and the clock enable signal is the first level, the first discharge unit is configured to discharge the first node to the first level.

4. The clock gating circuit of claim 2 , wherein in a case that the clock signal is the second level and the clock enable signal is the second level, the second discharge unit is configured to discharge the second node to the first level.

5. The clock gating circuit of claim 2 , wherein in a case that the second node is discharged to the first level, the first cross-coupled maintain unit is configured to maintain the first node at the second level.

6. The clock gating circuit of claim 2 , wherein in a case that the first node is discharged to the first level, the second cross-coupled maintain unit is configured to maintain the second node at the second level.

7. The clock gating circuit of claim 2 , wherein the control unit is configured to generate a control signal for controlling the first and second discharge units through a logic operation of voltage levels of the first and second nodes and the clock enable signal.

8. The clock gating circuit of claim 2 , wherein the first level is a low level and the second level is a high level.

9. The clock gating circuit of claim 1 , further comprising an inverting unit configured to invert the output clock signal,
wherein the control unit is configured to perform an OR operation on the clock enable signal and an output signal of the inverting unit, and an AND operation on a voltage level of the first node and a result value of the OR operation, to generate a control signal for controlling the first and second discharge units.

10. A clock gating circuit comprising:
a first transistor having a first end connected to a power supply node and a second end connected to a first node, the first transistor configured to be turned on according to a clock signal to charge the first node;
a second transistor having a first end connected to the power supply node and a second end connected to a second node at which an output clock signal is provided, the second transistor configured to be turned on according to the clock signal to charge the second node;
a third transistor having a first end connected to the power supply node and a second end connected to the first node, the third transistor configured to be turned on according to a voltage level of the second node to charge the first node;
a fourth transistor having a first end connected to the power supply node and a second end connected to the second node, the fourth transistor configured to be turned on according to a voltage level of the first node to charge the second node;
a fifth transistor configured to be turned on according to the clock signal;
a sixth transistor having a first end connected to a first end of the fifth transistor, is the sixth transistor configured to be turned on according to a voltage level of a third node to discharge the first node;
a seventh transistor having a first end connected to the second node and a second end connected to the third node, the seventh transistor configured to be turned on according to the clock signal to discharge the second node based on a voltage level of the third node; and
a control unit configured to control the voltage level of the third node based on a clock enable signal so that the first node or the second node is discharged,
wherein in a case that the fifth and sixth transistors are turned on, a second end of the fifth transistor and a second end of the sixth transistor are connected to the first node to discharge the first node.

11. The clock gating circuit of claim 10 , wherein in the case that a clock signal is a first level, the first and second transistors are turned on.

12. The clock gating circuit of claim 11 , wherein in a case that a level of the clock signal and the voltage level of the third node are a second level different from the first level, the fifth and sixth transistors are turned on.

13. The clock gating circuit of claim 12 , wherein in the case that a clock signal is the second level, the seventh transistor is turned on.

14. The clock gating circuit of claim 12 , wherein in a case that a voltage level of the second node is the first level, the third transistor is turned on and thereby the first node is maintained at the second level, and
wherein in a case that a voltage level of the first node is the first level, the fourth transistor is turned on and thereby the second node is maintained at the second level.

15. The clock gating circuit of claim 10 , wherein the control unit comprises:
a first control transistor having a first end connected to the power supply node and a second end connected to the third node, and having a gate at which a voltage level of the first node is applied;
a second control transistor having a first end connected to the third node, and having a gate at which the clock enable signal is applied;
a third control transistor having a first end connected to the power supply node and a second end connected to a second end of the second control transistor, and having a gate at which an inverted voltage level of the second node is applied;
a fourth control transistor having a first end connected to a ground node, and having a gate at which the voltage level of the first node is applied;
a fifth control transistor having a first end connected to the third node and a second end connected to a second end of the fourth control transistor, and having a gate at which the clock enable signal is applied; and
a sixth control transistor having a first end connected to the third node and a second end connected to the second end of the fourth control transistor, and having a gate at which the inverted voltage level of the second node is applied.

16. A clock gating circuit comprising:
a first precharge unit configured to charge a first node based on a clock signal;
a second precharge unit configured to charge a second node based on the clock signal;
a first discharge unit configured to discharge the first node based on the clock signal;
a second discharge unit configured to discharge the second node based on the clock signal;
a first cross-coupled maintain unit configured to maintain the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Hyunchul
• Kim Minsu

Classifications

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• G06F1/3237

  by disabling clock generation or distribution · CPC title

• H03K19/0016 Primary

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title