Apparatus for low power high speed integrated clock gating cell

Patent metadata

Field	Value
Publication number	US-9564897-B1
Application number	US-201615013659-A
Country	US
Kind code	B1
Filing date	Feb 2, 2016
Priority date	Oct 6, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

An apparatus for an integrated clock gating cell is provided. The apparatus includes a logic gate that receives an unbuffered enable signal (E), a scan test enable signal (SE), and outputs an inverted enable signal (EN); a first transmission gate that receives E, SE, and EN; a second transmission gate that is connected to the first transmission gate and receives a clock signal (CK) and an enabled and inverted clock signal (ECKN); a first transistor having terminals connected to a power supply voltage (VDD), an output of the logic gate, and the first transmission gate respectively; a second transistor including terminals connected to the first transmission gate and VDD respectively; and a latch including terminals connected to the second transmission gate and the second transistor respectively.

First claim

What is claimed is:

1. An integrated clock gating cell, comprising:
a logic gate, including a first input to receive an unbuffered enable signal (E), a second input to receive a scan test enable signal (SE), and an output that generates an inverted enable signal (EN);
a first transmission gate, including a first terminal for receiving E, a second terminal for receiving SE, a third terminal for receiving EN, a fourth terminal, and a fifth terminal;
a second transmission gate, including a first terminal connected to the fourth terminal of the first transmission gate, a second terminal connected to the fifth terminal of the first transmission gate, a third terminal for receiving a clock signal (CK), a fourth terminal for receiving an enabled and inverted clock signal (ECKN), and a fifth terminal; and
a first transistor, including a first terminal connected to a power supply voltage (VDD), a second terminal connected to the output of the logic gate, and a third terminal connected to the fourth terminal of the first transmission gate;
a second transistor, including a first terminal connected to the fifth terminal of the first transmission gate, a second terminal connected to VDD, and a third terminal; and
a latch, including a first terminal connected to the fifth terminal of the second transmission gate, a second terminal connected to the third terminal of the second transistor, and a third terminal.

2. The integrated clock gating cell of claim 1 , wherein the logic gate is a NOR gate.

3. The integrated clock gating cell of claim 1 , wherein the first transistor is a p-channel metal oxide semiconductor (PMOS) transistor and the second transistor is an n-channel metal oxide semiconductor (NMOS) transistor.

4. The integrated clock gating cell of claim 1 , wherein the first and third terminals of the first transistor and the second transistor are either a source terminal or a drain terminal, and wherein the second terminal of the first transistor and the second transistor are each a gate terminal.

5. The integrated clock gating cell of claim 1 , wherein the first transmission gate is comprised of:
a third transistor, including a first terminal for receiving E, a second terminal for receiving SE, and a third terminal; and
a fourth transistor, including a first terminal, a second terminal for receiving EN, and a third terminal connected to the first terminal of the third transistor.

6. The integrated clock gating cell of claim 5 , wherein the third transistor is a p-channel metal oxide semiconductor (PMOS) transistor and the fourth transistor is an n-channel metal oxide semiconductor (NMOS) transistor.

7. The integrated clock gating cell of claim 5 , wherein the first and third terminals of the third transistor and the fourth transistor are either a source terminal or a drain terminal, and wherein the second terminal of the third transistor and the fourth transistor are each a gate terminal.

8. The integrated clock gating cell of claim 1 , wherein the second transmission gate is comprised of:
a fifth transistor, including a first terminal connected to the third terminal of the third transistor, a second terminal for receiving a clock signal (CK), and a third terminal;
a sixth transistor, including a first terminal connected to the first terminal of the fourth transistor, a second terminal for receiving an enabled clock signal (ECKN), and a third terminal connected to the third terminal of the fifth transistor.

9. The integrated clock gating cell of claim 8 , wherein the fifth transistor is a p-channel metal oxide semiconductor (PMOS) transistor and the sixth transistor is an n-channel metal oxide semiconductor (NMOS) transistor.

10. The integrated clock gating cell of claim 1 , wherein the first and third terminals of the fifth transistor and the sixth transistor are either a source terminal or a drain terminal, and wherein the second terminal of the fifth transistor and the sixth transistor are each a gate terminal.

11. The integrated clock gating cell of claim 1 , wherein the latch is comprised of:
a third transistor, including a first terminal, a second terminal connected to the fifth terminal of the second transmission gate, and a third terminal connected to the third terminal of the second transistor;
a fourth transistor, including a first terminal connected to VDD, a second terminal for receiving ECKN, and a third terminal connected to the fifth terminal of the second transmission gate;
a fifth transistor, including a first terminal connected to VDD, a second terminal connected to the fifth terminal of the second transmission gate, and a third terminal connected to the first terminal of the third transistor;
a sixth transistor, including a first terminal connected to VDD, a second terminal for receiving CK, and a third terminal connected to the first terminal of the third transistor;
a seventh transistor, including a first terminal connected to the third terminal of the third transistor, a second terminal for receiving CK, and a third terminal connected to a ground; and
an inverter, including an input connected to the third terminal of the tenth transistor, and an output for generating an enabled clock signal (ECK).

12. The integrated clock gating cell of claim 11 , wherein the fourth transistor, the fifth transistor, and the sixth transistor are each a p-channel metal oxide semiconductor (PMOS) transistor and the seventh transistor and the eleventh transistor are each an n-channel metal oxide semiconductor (NMOS) transistor.

13. The integrated clock gating cell of claim 11 , wherein the first and third terminals of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are either a source terminal or a drain terminal, and wherein the second terminal of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are each a gate terminal.

14. An integrated clock gating cell, comprising:
a logic gate, including a first input to receive an unbuffered enable signal (E), a second input to receive a scan test enable signal (SE), and an output that generates an inverted enable signal (EN);
a first transistor, including a first terminal for receiving E, a second terminal for receiving SE, and a third terminal;
a second transistor, including a first terminal, a second terminal for receiving EN, and a third terminal connected to the first terminal of the first transistor;
a third transistor, including a first terminal connected to the third terminal of the first transistor, a second terminal for receiving a clock signal (CK), and a third terminal;
a fourth transistor, including a first terminal connected to the first terminal of the second transistor, a second terminal for receiving an enabled clock signal (ECKN), and a third terminal connected to the third terminal of the third transistor;
a fifth transistor, including a first terminal connected to a power supply voltage (VDD), a second terminal connected to the output of the logic gate, and a third terminal connected to the third terminal of the first transistor;
a sixth transistor, including a first terminal connected to the first terminal of the second transistor, a second terminal connected to VDD, and a third terminal;
a seventh transistor, including a first terminal, a second terminal connected to the third terminal of the third transistor, and a third terminal connected to the third terminal of the sixth transistor;
an eighth transistor, including a first terminal connected to VDD, a second terminal for receiving ECKN, and a third terminal connected to the

Assignees

• Berzins Matthew
• Lim James Jung
• Samsung Electronics Co Ltd

Inventors

• Berzins Matthew
• Lim James Jung

Classifications

• G06F1/04 Primary

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• H03K3/356147

  using pass gates · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K3/356052

  using pass gates · CPC title