Edge capacitive coupling for quantum chips

Patent metadata

Field	Value
Publication number	US-12249748-B2
Application number	US-202217935023-A
Country	US
Kind code	B2
Filing date	Sep 23, 2022
Priority date	Sep 23, 2022
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

A quantum computing chip device provides an edge based capacitive, intra-chip connection. A first chip includes a first signal line with a distal end positioned proximate to or on an edge of the first chip and a proximal end positioned away from the edge of the first chip. A second chip includes a second signal line with a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip. The first signal line and the second signal line are configured to conduct a signal. The second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip.

First claim

What is claimed is:

1. A quantum computing chip device, comprising:
a first chip including a first signal line including a distal end positioned proximate to or on an edge of the first chip, and a proximal end positioned away from the edge of the first chip;
a trench in a substrate of the first chip, wherein the first signal line is embedded in the trench; and
a second chip including a second signal line including a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip,
wherein the second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip; and
wherein the first signal line and the second signal line are configured to conduct a signal.

2. A quantum computing chip device, comprising:
a first chip including a first signal line including a distal end positioned proximate to or on an edge of the first chip, and a proximal end positioned away from the edge of the first chip; and
a second chip including a second signal line including a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip,
wherein the distal end of the first signal line is spaced from the edge of the first chip by a substrate material;
wherein the second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip; and
wherein the first signal line and the second signal line are configured to conduct a signal.

3. The quantum computing chip device of claim 1 , wherein the first signal line is positioned on a top surface of the first chip, over the edge of the first chip, and onto a sidewall mating surface of a first interposer.

4. The quantum computing chip device of claim 1 , further comprising a metallic chip coupled to the first signal line, wherein the metallic chip projects past the edge of the first chip and is disposed to provide the capacitive bus connection by a capacitance in cooperation with a second metallic chip coupled to the second signal line.

5. The quantum computing chip device of claim 1 , further comprising a capacitor pad on a distal end of the first signal line and adjacent to the edge of the first chip.

6. The quantum computing chip device of claim 5 , wherein the capacitor pad is embedded in a substrate of the first chip and spaced from the edge of the first chip.

7. The quantum computing chip device of claim 1 , further comprising a front face of the distal end of the first signal line, wherein the front face of the distal end of the first signal line is exposed through a side wall of the first chip.

8. The quantum computing chip device of claim 7 , wherein the front face of the distal end of the first signal line is flush with the side wall of the first chip.

9. The quantum computing chip device of claim 1 , further comprising a standoff on a side wall of the first chip.

10. The quantum computing chip device of claim 1 , further comprising a bump on a top surface of the first chip.

11. The quantum computing chip device of claim 1 , further comprising a first bump coupled to the first signal line, and disposed to provide capacitance in cooperation with a second bump positioned on the second signal line.

12. A quantum computing chip, comprising:
a substrate including a first end and a second end;
a first superconducting metal signal line including:
a first end positioned intermediate the first end of the substrate and the second end of the substrate, and
a second end positioned on an edge of the second end of the substrate;

a second superconducting metal signal line including:
a first end positioned intermediate the first end of the substrate and the second end of the substrate, and
a second end positioned proximate an edge of the second end of the substrate, wherein the first superconducting metal signal line and the second superconducting metal signal line are configured to generate a capacitive field; and

a metallic chip coupled to the first superconducting metal signal line and to the second end of the second superconducting metal signal line, and wherein one end of the metallic chip projects beyond the second end of the substrate.

13. A quantum computing chip, comprising:
a substrate including a first end and a second end;
a first superconducting metal signal line including:
a first end positioned intermediate the first end of the substrate and the second end of the substrate, and
a second end positioned on an edge of the second end of the substrate;

a second superconducting metal signal line including:
a first end positioned intermediate the first end of the substrate and the second end of the substrate, and
a second end positioned proximate an edge of the second end of the substrate, wherein the first superconducting metal signal line and the second superconducting metal signal line are configured to generate a capacitive field; and

one or more standoffs positioned on a side wall of the second end of the substrate.

14. The quantum computing chip of claim 13 , wherein the second end of the first superconducting metal signal line and the second end of the second superconducting metal signal line are positioned in a route extending from a top surface of the substrate, over the edge of the second end of the substrate, and over a side wall of the second end of the substrate.

15. The quantum computing chip of claim 13 , wherein the second end of the first superconducting metal signal line and the second end of the second superconducting metal signal line are exposed through the second end of the substrate.

16. The quantum computing chip of claim 13 , wherein the first superconducting metal signal line and the second superconducting metal signal line are embedded into the substrate.

17. The quantum computing chip of claim 13 , wherein the one or more standoffs are configured to provide a spacing based on a target capacitance in a coupling using the quantum computing chip.

18. A quantum computing chip, comprising:
a substrate including a first end and a second end;
a first superconducting metal signal line including:
a first end positioned intermediate the first end of the substrate and the second end of the substrate, and
a second end positioned on an edge of the second end of the substrate;

a second superconducting metal signal line including:
a first end positioned intermediate the first end of the substrate and the second end of the substrate, and
a second end positioned proximate an edge of the second end of the substrate, wherein the first superconducting metal signal line and the second superconducting metal signal line are configured to generate a capacitive field; and

a first conductive bump positioned on the first superconducting metal signal line and a second conductive bump positioned on the second superconducting metal signal line, wherein the capacitive field is formed between the first conductive bump and the second first conductive bump.

19. A method of manufacturing a quantum computing device, including:
forming a first chip substrate;
forming a first of one or more signal lines of a superconducting metal on a top surface of the first chip substrate, proximate to or in contact with, an edge of the top surface of the first chip substrate;
forming a second chip substrate;
forming a second of one or more signal lines of the superconducting metal on a top surface of the second chip

Assignees

• IBM

Inventors

• Kumph Muir
• Dial Oliver
• Cotte John Michael
• Abraham David

Classifications

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/657

  on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H01P11/003

  Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines · CPC title