Semiconductor structure

Patent metadata

Field	Value
Publication number	US-12249607-B2
Application number	US-202318152781-A
Country	US
Kind code	B2
Filing date	Jan 11, 2023
Priority date	Jun 29, 2021
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a carrier substrate;
a trap-rich layer, disposed on the carrier substrate;
a dielectric layer, disposed on the trap-rich layer;
an interconnect structure, disposed on the dielectric layer;
a device structure layer, disposed on the interconnect structure and electrically connected to the interconnect structure; and
a circuit structure, disposed on the device structure layer and electrically connected to the device structure layer,
wherein the interconnect structure is not in contact with the trap-rich layer, and the interconnect structure is located between the dielectric layer and the device structure layer.

2. The semiconductor structure of claim 1 , wherein the trap-rich layer comprises a polysilicon layer, an amorphous silicon layer, a silicon nitride layer, a silicon carbon nitride layer or a combination thereof.

3. The semiconductor structure of claim 1 , wherein a thickness of the trap-rich layer is between 3000 Å and 20000 Å.

4. The semiconductor structure of claim 1 , wherein the dielectric layer comprises an oxide silicon layer.

5. The semiconductor structure of claim 1 , wherein a thickness of the dielectric layer is between 2000 Å and 8000 Å.

6. The semiconductor structure of claim 1 , wherein the carrier substrate comprises a silicon substrate.

Assignees

• United Microelectronics Corp

Inventors

• Zhang Sheng
• Qi Chunyuan
• Chen Xingxing
• Pang Chien-Kee

Classifications

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title